Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-26
2003-07-29
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S155000, C257S328000, C257S329000, C257S330000, C257S331000, C257S334000
Reexamination Certificate
active
06600182
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to field-effect semiconductor transistor structures with high current capability.
BACKGROUND OF THE INVENTION
In the past several years, trench-based vertical MOSFET devices have emerged as a dominant technology for high power applications. These devices can achieve a relatively high blocking voltage in the off state while minimizing the resistance to current flow in the “on” state using high cell density. The acronym Rds(on)×A refers to the product of the resistance and surface area, and is generally used to describe the on-state performance of the device. It is well known that these devices can achieve a low Rds(on) and a relatively high voltage blocking. An example of a trench-based vertical MOSFET power device is found in U.S. Pat. No. 5,998,833.
One of the problems, however, with these trench devices is that they suffer from increased gate capacitance and Miller capacitance, which negatively affects device operation at high frequencies. This results in a proportional increase in the switching (AC) power losses at high frequency.
Lateral MOSFET devices have a much lower drain-to-gate overlapping and therefore a much lower Miller capacitance as compared with vertical devices. In general, lateral devices also have a comparable on-state resistance to that of vertical structures, but with lower parasitic capacitance values. Hence, lateral MOSFETS are usually better suited for high frequency operations. For instance, lateral MOSFETs are commonly used in RF and microwave amplifiers operating in the gigahertz (GHz) frequency range. Examples of traditional lateral MOSFET device structures for power applications include U.S. Pat. Nos. 5,869,875, 5,821,144, 5,760,440, and 4,748,936.
Traditionally designed lateral MOSFETs have a P+ region near the source, often called a sinker. The purpose of the sinker is to provide a good contact to the P-body region under the source for more efficient hole collection. This relatively deep P+ region protrudes through the epitaxial region and reaches into the P+ substrate. U.S. Pat. Nos. 5,869,875 and 5,821,144 teach replacing the relatively wide P+ sinker diffusion in a traditional DMOS structure with either a conducting trench or a partial trench with a P+ sinker diffusion region. The result is a smaller cell size and lower on resistance. However, the drain electrode structure limits the current conduction capability in these structures, since current flows only through narrow metal drain strips.
U.S. Pat. No. 4,748,936 also discloses a MOS device with a trench in the epitaxial layer that also suffers from drain current flow through the metal formed of stripes to the appropriate wire bonding area. In this approach, like the others described above, improvement in the lateral device relates to cell area reduction. This area reduction is achieved by replacing the diffused sinker area (that consumes a lot of area connecting the source to the substrate) with an etched trench structure. One of the chief drawbacks, however, of the aforementioned device structures is that they do not provide for adequate high current conduction.
The device structure taught in U.S. Pat. No. 5,760,440 does provide improved current conduction in a lateral MOSFET transistor; however, the teaching of this patent is limited to n-channel transistors having a N+ substrate and a P-type epitaxial structure. As a result, the P-type epitaxial region is not effectively connected to the source region and there is a problem with hole extraction from the P-body under the source. One consequence of this is that the device structure suffers from weak safe operating area (SOA) performance level and poor reliability.
Thus, there is an unsatisfied need for a transistor device structure that solves the problem of high parasitic Miller capacitance inherent in vertical devices, and which at the same time overcomes the low current conduction problem normally associated with lateral devices, as well as provide a high safe operating/reliability level. In other words, what is needed is a power transistor that provides improved high frequency operation at high current densities.
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Jun Cai, Changhong Ren, et al. , High Performance Stacked LDD RF LDMOSFET, Proceedings of 2001 International Symposium on Power Semiconductor Devices & PCs, Osaka, Japan; pp. 103-106.*
High Performance Stacked LDD RFLDMOSFET, Jun Cai, Changhong Ren, et al., Proceedings of 2001 International Symposium on Power Semiconductor Devices & PCs, Osaka, Japan; pp. 103-106.
Burgess & Bereznak LLP
Tran Mai-Huong
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