Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2005-12-20
2005-12-20
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S081000, C326S083000, C327S534000, C361S111000, C361S056000
Reexamination Certificate
active
06977524
ABSTRACT:
Using at best a 2.5V nominal power supply, 3.3V technology can be used to implement a 5V tolerant open drain output buffer. High voltage and/or current tolerance is achieved with only the 2.5V power supply. A p-channel FET transistor is connected between a power supply and a node, which in turn is connected to a node between two series output FET transistors. The first transistor is connected between the PAD and node, and the second transistor is connected between the node and ground. The gate of the second transistor is driven from another node formed between a series string of a p-channel FET transistor and an n-channel FET transistor. The other side of the first transistor is connected to the power supply, and the other side of the second transistor is connected to ground. The gates of the transistors of the inverter are tied together and driven by an applied signal.
REFERENCES:
patent: 5684415 (1997-11-01), McManus
patent: 5852450 (1998-12-01), Thingvold
patent: 6236236 (2001-05-01), Chen
patent: 6342803 (2002-01-01), McManus
patent: 6369619 (2002-04-01), Kawa et al.
patent: 6496054 (2002-12-01), Prather et al.
Huber Carol Ann
Kothandaraman Makeshwar
Morris Bernard Lee
Smooha Yehuda
Agere Systems Inc.
Tan Vibol
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