High capacitive load and noise tolerant system and method...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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Details

Other Related Categories

C326S087000, C327S108000

Type

Reexamination Certificate

Status

active

Patent number

07782080

Description

ABSTRACT:
An output driver calibration circuit includes a programmable drive strength output pullup driver including a strongest transistor and a number of other transistors, a programmable drive strength output pulldown driver including a strongest transistor and a number of other transistors, and a calibration circuit for generating a number of control signals for controlling the transistors in the output pullup driver and the transistors in the output pulldown driver, wherein the control signals are generated simultaneously, except for two the strongest driver transistors.

REFERENCES:
patent: 5666078 (1997-09-01), Lamphier et al.
patent: 6307791 (2001-10-01), Otsuka et al.
patent: 6661250 (2003-12-01), Kim et al.
patent: 6919738 (2005-07-01), Kushida
patent: 2007/0089440 (2007-04-01), Singh et al.

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