High capacitive density stacked decoupling capacitor structure

Details High capacitive density stacked decoupling capacitor structure High capacitive density stacked decoupling capacitor structure

2005-11-29

2005-11-29

Trinh, Michael (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S310000, C257S532000, C438S393000, C438S250000, C438S239000

Reexamination Certificate

active

06969880

ABSTRACT:
A capacitive structure (10). The capacitive structure comprises a semiconductor base region (30) having an upper surface, a well (12) formed within the semiconductor base region and adjacent the upper surface, a first dielectric layer (38) adjacent at least a portion of the upper surface, and a polysilicon layer (16) adjacent the first dielectric layer. The well, the first dielectric layer, and the first polysilicon layer form a first capacitor and are aligned along a planar dimension. The capacitive structure further comprises a first conductive layer (201) positioned with at least a portion overlying at least a portion of the polysilicon layer, a second dielectric layer (202) adjacent the first conductive layer, and a second conductive layer (203) adjacent the second dielectric layer. The first conductive layer, the second dielectric layer, and the second conductive layer form a second capacitor and are aligned along the planar dimension.

REFERENCES:
patent: 5851868 (1998-12-01), Kim
patent: 5998264 (1999-12-01), Wu
U.S. Appl. No. 10/335,333, filed Dec. 31, 2002, S.S. Papa Rao et al.
U.S. Appl. No. 10/638,596, filed Aug. 11, 2003, S.S. Papa Rao et al.

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