Stock material or miscellaneous articles – Structurally defined web or sheet – Nonplanar uniform thickness material
Reexamination Certificate
1997-06-19
2002-05-21
VerSteeg, Steven H. (Department: 1753)
Stock material or miscellaneous articles
Structurally defined web or sheet
Nonplanar uniform thickness material
C428S141000, C430S011000, C430S014000
Reexamination Certificate
active
06391426
ABSTRACT:
DESCRIPTION
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the manufacture of capacitors in silicon substrates and has particular application to the manufacture of dynamic random access memories (DRAMs) in semiconductor devices.
2. Background Description
DRAM semiconductor devices use a capacitor in each memory cell in order to store information. In order to optimize the density and performance of these devices, it is desirable to create as high a capacitance as possible in the smallest area of silicon. Deep trench capacitors and stacked capacitors are two types of capacitor structures which are commonly used in industry. Deep trench capacitors are formed by printing a small opening in a resist using photoresists, lithographic patterning technologies, and etching. Typically, a trench of 5-15 &mgr;m deep is etched into a wafer, chip, or similar substrate using the patterned photoresist as a mask when fabricating deep trench capacitors. The sidewalls of this trench are coated with a dielectric and then filled with polysilicon in order to form the capacitor. Stacked capacitor structures are formed on the surface of the wafer or chip substrate by creating upward-reaching protrusion of a conductive material coated with a dielectric. The upward protrusion is often formed by printing a small space in a resist, etching the space pattern into an underlying dielectric, and then coating the etched opening with polysilicon. The problem with these two approaches is that it is difficult to etch the trench deep enough, or make the protrusions tall enough, to generate a desirable capacitance.
Several methodologies have been developed for increasing capacitance. For example, some methods have used standing waves in the resist pattern to provide additional surface area for the stacked capacitor (see, for example, U.S. Pat. No. 5,556,802 to Wong et al.). Other methods have also been used to increase the surface area of the capacitor (see, for example, Morihara et al., “Disk-Shaped Stacked Capacitor Cell for 256 Mb Dynamic Random Access Memory”,
Jap. J. Appl. Phys.,
33:4570-4575 (August, 1994); Nguyen, S. V. et al., “Novel Fingered Stack Capacitor Cell”,
J. Electrochem. Soc.,
142:L111-L113 (July, 1995); and “Toshiba's New Capacitor Structure for its 1 Gb DRAM Memory Cell”,
Microelectronics Journal
, Vol. 27, page vi, March-June, 1996). Techniques have also been developed for the etching of higher aspect ratio structures in substrates. Furthermore, some methodologies have involved the formation of dielectric layers with materials of high dielectric constant. Examples of these techniques and methodologies can be found in Matsuo, N. et al., “Higher-Integrated Spread-type Stacked Capacitor and Its Suitable Arsenic Solid-Diffusion Method”,
Microelectronics J.
27:73-77 (February, 1996); Ohji et al., “Ta
2
O
5
Capacitor Dielectric Material for Gigabit DRAMs”,
Proc.
1995
International, Electron Devices Meeting, IEEE
, Piscataway, N.J. 95CH35810, pages 111-114; and Kwon et al., “Ta
2
O
5
Capacitors for 1 Gbit DRAM and Beyond”,
Proc.
1994
IEEE International Electron Devices Meeting,
94CH35706, pages 835-838.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a simple and effective fabrication method for fabricating high capacitance storage node structures such as DRAMs or the like.
It is another object of this invention to provide a technique for increasing the polysilicon surface in a capacitor structure to substantially increase capacitance, without etching deeper into a wafer or forming taller protrusions;
It is yet another object of this invention to provide novel structures having high capacitance storage nodes.
According to the invention, a hybrid resist is positioned on top of the substrate in which the high capacitance storage node is to be created. The hybrid resist acts as a positive tone at low exposure doses and a negative tone at high exposure doses. When the resist is image-wise exposed with a storage capacitor pattern, the features which normally print as a simple resist opening, actually print as an opening with an island of resist in the center. This is because the resist which forms the center island is exposed to relatively more radiant energy and acts as a negative tone, while the resist surrounding the center island is exposed to relatively less radiant energy and acts as a positive tone. After exposure, the resist in the exposed positive tone region is removed. The pattern is then transferred to the underlying substrate by etching the substrate using the resist as a mask. This creates a center protrusion within the etched trench which underlies the center island negative tone resist. This protrusion provides additional surface area within the capacitor which provides an approximately 2× increase in capacitance in a fully fabricated DRAM capacitor. The process is useful in fabricating both deep trench capacitors and stacked capacitors. It is simpler to perform than processes which require multiple deposition and etch processes. Furthermore, the process can be used in conjunction with other capacitance enhancing techniques such as higher aspect ratio structures, use of higher dielectric constant insulating materials, and use of standing waves in the resist pattern.
REFERENCES:
patent: 4671970 (1987-06-01), Keiser et al.
Hakey Mark C.
Holmes Steven J.
Horak David V.
Ma William H.
Chadurjian Mark F.
VerSteeg Steven H.
Whitham Curtis & Christofferson, P.C.
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