High capacitance multi-level storage node for high density TFT l

Details High capacitance multi-level storage node for high density TFT l High capacitance multi-level storage node for high density TFT l

1994-08-11

1995-06-20

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257382, 257532, 257903, 365182, H01L 2702, G11C 1100, G11C 1134

Patent

active

054263247

ABSTRACT:
A high capacitance multi-level storage node contact is proposed for high density SRAMs. The proposed contact connects several poly levels to diffusion and to a trench capacitor, in one contact. The high storage node capacitance provided by the trench capacitor substantially reduces the soft error rate probability of the cell. The use of a single contact to connect several levels reduces the area. The contact preferably uses TiN as a barrier layer to reduce dopant diffusion between different poly layers.

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patent: 5204279 (1993-04-01), Chan et al.
"High Density SRAM Structure with a New Three-Dimensional, High- . . . " J. P. Gambino et al IBM Tech. Disc. Bul. vol. 34 #2 Jul. 1991 pp. 255-258.
"High-Density CMOS SRAM Cell" W. H. Chang IBM Tech. Disc. Bulletin v. 34 #6 Nov. 1991 pp. 95-96.
"High Density Thin Film Transistor Load SRAM Cell Using Trench . . . " T. V. Rajeevakumar IBM Tech. Disc. Bul. v. 36 #09A Sep. 1993 pp. 581-582.

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