Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1994-09-27
1996-04-30
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257355, 257336, 257343, 257344, 257408, 257409, H01L 2994, H01L 31062, H01L 31113, H01L 31119
Patent
active
055127690
ABSTRACT:
A high breakdown voltage semiconductor device is constituted, in either a semiconductor substrate or a lightly doped well diffused layer having deep diffusion depth, of a heavily doped diffused layer as a heavily doped drain diffused layer, a lightly doped diffused layer having deeper diffusion depth that the heavily doped diffused layer, and a lightly doped diffused layer adjacent to the heavily doped diffused layer called as an offset diffused layer. The heavily doped diffused layer functions as a part of the drain diffused layer, and has depth around 0.3 to 0.6 micron meter, and impurity concentration of 10.sup.19 to 10.sup.20 impurities/cm.sup.3. The width of the heavily doped diffused layer is set to 4 to 5 micron meters or greater. If the width of the heavily doped diffused layer is set less than this value, the breakdown voltage at an edge is lowered, and thereby impairment of the breakdown voltage occurs. The lightly doped diffused layer also functions as a part of the drain diffused layer. The lightly doped diffused layer is arranged, in particular, to relax the gradient of the impurity concentration of the drain diffused layer due to the heavily doped diffused layer. If the impurity concentration of the lightly doped diffused layer is too low, the resistance becomes high, so that adequate current can not be obtained. In the high breakdown voltage transistor, a gate electrode is formed above the edge of the lightly doped diffused layer. The breakdown voltage of the device is determined by the size of the offset diffused layer and its impurity concentration.
REFERENCES:
patent: 4878100 (1989-10-01), McDavid
patent: 5061649 (1991-10-01), Takenouchi et al.
patent: 5191401 (1993-03-01), Shirai et al.
Ratnam et al., "Drain Engineering of Hot-Corner-Resistant MOSFETs Using Concave Silicon Surfaces for Deep Submicron VLSI Technology," Solid--State Electronics, vol. 33, No. 9, 1990, pp. 1163-1168.
Crane Sara W.
Matsushita Electronics Corporation
Tang Alice W.
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