Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-21
2003-09-09
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S488000, C257S492000, C257S496000
Reexamination Certificate
active
06617652
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a high breakdown voltage semiconductor device.
A conventional high breakdown voltage semiconductor device is disclosed, for example, in Japanese Laid-Open Patent Publication No. 2000-12854. The high breakdown voltage semiconductor device disclosed in this publication is an insulated gate transistor. Hereinafter, a conventional insulated gate transistor will be described with reference to FIG.
12
.
FIG. 12
schematically shows a cross-sectional structure of a conventional insulated gate transistor.
The insulated gate transistor shown in
FIG. 12
includes a p-type semiconductor substrate
1
, a drain offset diffusion region
2
containing a low concentration of n-type impurities formed in the semiconductor substrate
1
, a low concentration buried diffusion region
3
containing p-type impurities buried in the drain offset diffusion region
2
, a drain diffusion region
4
containing a high concentration of n-type impurities located in the drain offset diffusion region
2
, a source diffusion region
5
containing a high concentration of n-type impurities formed in the semiconductor substrate
1
, and a diffusion region
19
for contact containing a high concentration of p-type impurities. The low concentration buried diffusion region
3
serves to promote the depletion of the drain offset diffusion region
2
when a high voltage is applied to the drain. Although not shown in
FIG. 12
, a part of the low concentration buried diffusion region
3
is connected to the semiconductor substrate
1
. A diffusion region
20
for preventing a punch-through containing p-type impurities is formed in the semiconductor substrate
1
so as to enclose the source diffusion region
5
and the diffusion region
19
for contact. The diffusion region
20
for preventing a punch-through serves to increase the concentration of the p-type impurities between the drain offset diffusion region
2
and the source diffusion region
5
, which are the active regions of an MOS transistor, to prevent a punch-through phenomenon between them.
A thin gate oxide film
6
and a thick oxide film (field oxide film)
7
are formed on the semiconductor substrate
1
. A gate electrode
11
made of polysilicon is provided on a portion of the oxide film
6
or
7
on the portion between the drain offset diffusion region
2
and the source diffusion region
5
. A drain polysilicon electrode
18
is formed on a portion of the oxide film
6
or
7
that is positioned on a portion between the drain offset diffusion region
2
and the drain diffusion region
4
. An interlayer insulating film
8
is formed so as to cover the oxide films
6
and
7
, the gate electrode
11
, and the drain polysilicon electrode
18
.
Metal electrodes
12
,
13
and
14
are connected to the diffusion region
19
for contact, the source diffusion region
5
and the drain diffusion region
4
, respectively. The metal electrode
12
is a metal electrode for a body to be connected to the p-type semiconductor substrate
1
, which is a body. The metal electrode
13
is a metal electrode for a source for contact with the source diffusion region
5
. The metal electrode
14
is a metal electrode for a drain for contact with the drain diffusion region
4
. A surface protective film
9
is formed on the metal electrodes
12
,
13
and
14
and the interlayer insulating film
8
. A resin for sealing
10
is formed thereon.
In the insulated gate transistor shown in
FIG. 12
, a GND potential is supplied to the metal electrode
13
for a source, the metal electrode
12
for a body, and the low concentration p-type buried diffusion region
3
. A positive high potential is supplied to the metal electrode
14
for a drain. A control voltage is supplied to the gate electrode
11
. When a positive potential (control voltage) of a threshold or more is supplied to the gate electrode
11
, an inversion from the p-type to the n-type occurs in the vicinity of the surface of the semiconductor substrate
1
immediately below the gate electrode
11
, and thus a so-called channel region is generated so that the insulated gate transistor becomes conductive. The conducted current in this case flows from the drain diffusion region
4
through the drain offset diffusion region
2
and the channel region on the surface of the semiconductor substrate
1
to the source diffusion region
5
. On the other hand, when the voltage of less than a threshold is supplied to the gate electrode
11
, the channel region becomes small, so that the insulated gate transistor becomes non-conductive.
In this specification, maintaining the non-conductive state in a transistor is defined as “having a breakdown voltage”, and maintaining the non-conductive state in a transistor at a high bias voltage (e.g., 100 V or more) is defined as “having a high breakdown voltage”. The resistance value between the source and the drain while a transistor is conductive is defined as “ON resistance”.
Next,
FIG. 13
is referred to.
FIG. 13
shows the potential distribution when a high voltage (600 V) is supplied to the high breakdown voltage semiconductor device (insulated gate transistor) shown in
FIG. 12
at room temperature, and an equipotential line for each potential is indicated by a broken line. This potential distribution (equipotential lines) is obtained based on the results of simulation by the inventors of the present invention.
The potential distribution shown in
FIG. 13
is one obtained when 0(V) is supplied to the p-type semiconductor substrate
1
, the p-type low concentration buried diffusion region
3
, and the n-type source diffusion region
5
; 0(V) is supplied to the gate electrode
11
; and 600 (V) is supplied to the n-type drain diffusion region
4
. The equipotential lines in this case are shown by broken lines.
The high breakdown voltage semiconductor device shown in
FIG. 12
utilizes a technique called “resurf” for depleting the entire drain offset diffusion region
2
to ensure an initial breakdown voltage. The principle thereof will be described below.
To operate this high breakdown voltage semiconductor device, in general, 0 (V) is supplied to the semiconductor substrate
1
and the source diffusion layer region
5
, and a drain voltage necessary for operation is supplied to the metal electrode
14
. When the drain voltage is gradually increased from 0 (V), while the drain voltage is low, a depletion layer stemming from the pn junction between the p-type semiconductor substrate
1
and the n-type drain offset diffusion region
2
extends into the p-type semiconductor substrate
1
and the drain offset diffusion region
2
, and a depletion layer stemming from the pn junction between the p-type low concentration buried diffusion region
3
and the drain offset diffusion region
2
extends into the low concentration buried diffusion region
3
and the drain offset diffusion region
2
. In FIG.
13
, the concentration distribution in the vertical direction of the low concentration buried diffusion region
3
is such that the concentration of the central portion is high, and the concentration is decreased as being apart from the central portion in the upward or downward direction. Therefore, the potential in the vertical direction in the low concentration buried diffusion region
3
is distributed such that the potential is kept low in the central portion.
Furthermore, 0 (V) is set in the portion on the source side in the low concentration buried diffusion region
3
, and the region extends to the drain side, so that the potential in the low concentration buried diffusion region
3
in the horizontal direction is distributed such that the potential increases in the direction from the source to the drain. Therefore, as shown in
FIG. 13
, the equipotential lines in the low concentration buried diffusion region
3
have a projection to the drain side.
Next, as the drain voltage is increased, the depletion layer extending from the pn junction between the semiconductor substrate
1
and the drain offset diffusion region
2
is j
Ho Tu-Tu
Nelms David
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