High breakdown voltage junction terminating structure

Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – In integrated circuit

Reexamination Certificate

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Details

C257S491000, C257S487000, C257S493000

Reexamination Certificate

active

07135751

ABSTRACT:
A high breakdown voltage junction terminating structure having a loop-like RESURF structure formed on a SOI substrate is disclosed. A lateral IGBT, a lateral FWD, an output stage element and a driving circuit are formed in the inside region of the structure. The lateral IGBT and the lateral FWD are surrounded by a trench isolation region as an insulation region. Drain electrodes of high breakdown voltage NMOSFETs are provided on the inside of the high breakdown voltage junction terminating structure. Along with this, a gate electrode and a source electrode of each of the NMOSFETs are provided on the outside of the high breakdown voltage junction terminating structure. The periphery of the high breakdown voltage junction terminating structure is surrounded by a trench isolation region as a second insulation region. A control circuit is provided on the outside of the second insulation region. With this structure, a high breakdown voltage semiconductor device is obtained at low cost, in which power elements, circuits for driving the power elements and logic elements for controlling the power elements are integrated together into the same chip.

REFERENCES:
patent: 5801418 (1998-09-01), Ranjan
patent: 6124628 (2000-09-01), Fujihira et al.
patent: 2002-33382 (2002-01-01), None
patent: 2002-83935 (2002-03-01), None
patent: 2002-118234 (2002-04-01), None
patent: 2002-246551 (2002-08-01), None
patent: 2003-17503 (2003-01-01), None
patent: 2003-17704 (2003-01-01), None
Fujihira et al., “Self-shielding: New High-Voltage Inter-Connection Technique for HVICs”, IEEE,0-7803-3106-0, 1996, pp. 231-234, (Reference submitted in IDS of Jul. 21, 2004).
T. Fujihira et al.; “Self-shielding: New High-Voltage Inter-Connection Technique for HVICs”; IEEE, 0-7803-3106-0, 1996; pp. 231-234.

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