High bandwidth narrow I/O memory device with command stacking

Details High bandwidth narrow I/O memory device with command stacking High bandwidth narrow I/O memory device with command stacking

1998-05-15

2000-05-16

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711104, 711167, 710107, 710118, G06F 1300

Patent

active

060650931

ABSTRACT:
A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.

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