High bandwidth memory interface

Details High bandwidth memory interface High bandwidth memory interface

2007-11-20

2007-11-20

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000

Reexamination Certificate

active

10919491

ABSTRACT:
This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device.

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