High bandwidth DRAM with low operating power modes

Details High bandwidth DRAM with low operating power modes High bandwidth DRAM with low operating power modes

1998-07-24

2001-01-23

Chan, Eddie P. (Department: 2751)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C711S005000, C711S105000, C365S230020, C365S230030, C710S120000

Reexamination Certificate

active

06178517

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to high bandwidth/performance Dynamic Random Access Memories (DRAMs) and, more particularly, to high bandwidth/performance DRAMs with low power operating modes.
2. Description of the Related Art
Dynamic random access memory (DRAM) performance is a well known limitation to computer system performance. Processor speeds are rapidly outpacing main memory performance, with both processor designers and system manufacturers developing higher performance memory subsystems in an effort to minimize performance limitations due to the slower DRAM devices. Ideally, the memory performance would match or exceed processor performance, i.e., a memory cycle time would be less than one processor clock cycle. This is almost never the case and, so, the memory is a system bottleneck. For example, a state of the art high speed microprocessor may be based on a 200 MegaHertz (MHZ) clock with a 5 nanosecond (ns) clock period. A high performance DRAM may have a 60 ns access time, which falls far short of processor performance.
This system bottleneck is exacerbated by the rise in popularity of multimedia applications. Multimedia applications demand several times more bandwidth for main memory or frame-buffer memory than computational intensive tasks such as spread sheet analysis programs or, other input/output (I/O) intensive applications such as word processing or printing.
Extended Data Out (EDO) and Synchronous DRAMs (SDRAMs) were developed to improve bandwidth. However, SDRAMs and EDO RAMs still do not match processor performance and, therefore, still limit system performance. Consequently, as faster microprocessors are developed for multimedia processing and high performance systems, faster memory architecture is being developed to bridge the memory/processor performance gap, e.g., wide I/O DRAMs.
Recent developments predict a major turning point for memory devices and related subsystems with a shift to high speed
arrow I/O devices. These high bandwidth (data rate) DRAMs achieve the high data rate by accessing a large number of bits in an array, then multiplexing by 8:1 to achieve clocked data rates in excess of 500 MHZ.
For example, referring to
FIG. 1
, there is shown a high speed I/O DRAM memory device of the type sought to be improved by the present invention. A 64 Mb memory array comprises four 16 Mb (64×256×1024) sub-arrays
10
,
12
,
14
, and
16
. Each of the sub-arrays are buffered by a page register
20
,
22
,
24
, and
26
, respectively. The page registers are organized as 64×256 bit addresses (i.e., 2 Kb). Data to and from the page registers
20
,
22
,
24
, and
26
are transferred on a sixty-four bit bus
30
from driver
32
or buffer
34
. Buffer
34
passes data from the sixty-four bit bus
30
to an 8:1 multiplexer (MUX)
36
and, in turn, the multiplexer
36
passes the data off chip to I/O pins
38
DQ
0
-DQ
8
. The sixty-four bit bus
30
permits eight bursts of eight bits. Similarly, data in from the I/O pins
38
are received by a 1:8 demultiplexer (DEMUX)
40
which, under the control of control logic
42
and data mask register
44
, is passed by the driver
32
to the sixty-four bit-bus
30
. In a page read operation, the first access row address and commands are piped into the control logic
42
via the I/O pins
38
DQ
0
-DQ
8
in parallel. For a given address, it will require eight bursts of eight-bit bytes to read out the sixty-four bit wide page register. During this time, the next column address and commands are serially scanned into the address pin
46
and command
47
pin, one bit at a time for eight successive clock cycles, until a new command/data packet is scanned in. RXCLK and TXCLK are used for external handshaking.
The above high bandwidth approach achieves the high data rate by accessing a large number of bits in an array resulting in high power dissipation requirements. For systems with a battery power option, this large power dissipation severely limits battery life. For high resolution graphics displays, the high data rate is needed. However, for many applications, such word processors, spreadsheets, etc., it is not necessary to operate at such high rates and high power usage.
Thus, there is a need in the art for a DRAM memory which operates in either a high bandwidth mode or low power mode while maintaining a constant clock frequency.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a high speed
arrow I/O dynamic random access memory (DRAM) which operates at a high bandwidth mode for accommodating, for example, graphic intensive applications, or in a low power mode for accommodating, for example, word processing or spreadsheet applications.
It is yet another object of the present invention to provide a high speed
arrow I/O DRAM where the speed/power mode can be adjusted to accommodate various applications.
According to the present invention, a high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHz) 8:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.
Each of the two bus networks may be completely separate or may share bus lines. For example, the slower bus may be 64-bits wide and the high-speed bus only 8-bits wide. Alternatively, the slower bus may be 56-bits wide. In this case in a high bandwidth mode, both the 56-bit bus and the 8-bit bus are utilized to accommodate the transfer of 64 bits between the DRAM and the processor for low power operation. In either case the processor selects the appropriate bus or combination of busses to accommodate the needs of the current application. This may be accomplished via processor generated instructions to a chip set.


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Prince, Betty. High Performance Memories: New Architecture DRAMs and SRAMs—Evolution and Function. 1996. pp. 212-227.

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