Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-04-24
2001-01-16
Bragdon, Reginald G. (Department: 2751)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S218000, C711S167000, C711S005000
Reexamination Certificate
active
06175893
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to the field of disk drive controllers. More particularly, the present invention pertains to disk drive microcontrollers, read only program code memory and the interface therebetween.
2. Description of the Related Art
If the speed at which a microcontroller executes program code words is matched by the speed at which the memory storing these program code words is able to provide them, then the microcontroller and code memory are evenly matched. Under such a state, the microcontroller requests a program code word from the code memory by supplying the code memory with the address of the program code word requested. The code memory then decodes the address and supplies the microcontroller with the program code word located at the address supplied by the microcontroller as soon as the microcontroller is able to process it.
However, a problem arises when the microcontroller processes instruction code words faster than the code memory is able to supply them. The speed of the code memory then becomes a bottleneck, limiting the rate at which the microcontroller processes instructions to the rate at which the code memory is able to supply the program code words. Under these circumstances, the microcontroller is forced to wait in an idle state for code words to appear on its data bus from the slower code memory, without executing any instructions. The clock cycles during which the microcontroller waits for the slower code memory to place requested program code words on the data bus are appropriately called wait states.
It has become apparent that the speed of microcontrollers has outpaced the speed of read only memories, the type of memory typically used to store program code words. A number of palliative measures have been adopted to attempt to address this disparity in operating speeds. One such measure is simply to insert a predetermined number of wait states, during which the microcontroller is idle, waiting for a next program code word to be placed on its data bus from the read only memory. This is, however, a less than optimal solution, as microcontroller resources are not efficiently utilized.
Another measure that has been proposed divides the code memory into two banks of memories; namely, one memory bank for storing code words whose addresses are odd and another memory bank for storing code words whose addresses are even. This is commonly called interleaved memory. Using interleaved even and odd memories, Yamada, in U.S. Pat. No. 5,594,888, speeds up read operations of a program stored in a ROM by simultaneously latching an odd byte and the next consecutive even byte (or vice-versa) of a multi-byte instruction word from the odd and even memory banks, respectively, responsive to two read signals. However, such an approach appears limited to retrieving consecutive bytes of a single multi-byte instruction and appears to require the re-generation of a code word address for each new instruction. Moreover, this approach requires complex signaling, additional signal pins on the device and yields only an incremental improvement in microcontroller utilization, and then only for multi-byte instructions. The problem of how to efficiently supply code words from a slow code memory to a relatively faster microcontroller remains unsolved.
What is needed, therefore, is a means for efficiently supplying program code words from a slow code memory to a relatively faster microcontroller. In particular, what is needed is a means for supplying a microcontroller with the requisite program code words from a relatively slower code memory that does not require the microcontroller to generate addresses for linear code.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide circuits for efficiently supplying code words from a slow code memory to a relatively faster microcontroller.
It is another object of the present invention to provide circuits for supplying a microcontroller with the requisite program code words from a relatively slower code memory, without requiring the microcontroller to insert one or more wait states.
In accordance with the above objects, a read-only memory according to an embodiment of the present invention is connectable to a microcontroller data bus and address bus, and comprises memory circuits for storing a sequential array of code words executable by the microcontroller; memory address decoding circuits for selecting one code word of the array of code words; circuits for conveying the selected one code word to the data bus when a read signal is received from the microcontroller; circuits for storing an address transmitted on the address bus by the microcontroller when an address latch signal is asserted by the microcontroller, the stored address being connected to the memory address decoding circuits; and circuits for incrementing the stored address each time a read signal is received from the microcontroller.
The read-only memory may further comprise a ready circuit having a ready state and a not-ready state for delaying the microcontroller when the not-ready state is asserted. The not-ready state may be asserted by the ready circuit when a read signal is received immediately after an address is stored. The ready state may be asserted by the ready circuit immediately when a read signal is received subsequent to a read operation from the stored address. The memory circuits may comprise an odd array and an even array. The address storing circuits may comprise odd address storage circuits connected to the odd array and even address storage circuits connected to the even array. The stored address incrementing circuits, according to the present invention, may increment the even address storage circuits when the address transmitted by the microcontroller is odd.
Another embodiment of the present invention is a microcontroller for executing a program stored sequentially in a read-only memory, the microcontroller comprising an address bus for providing a next program code word address to the read-only memory; circuits for providing an address latch enable signal to the read-only memory for latching the program code word address; circuits for providing a read signal to the read-only memory; and circuits for suppressing the address latch enable signal when the next program code word address is consecutive with an immediately preceding program code word address.
A further embodiment of the present invention is a disk drive having a controller, the controller comprising a read only memory and a microcontroller for executing a program stored sequentially in the read-only memory, wherein the microcontroller includes an address bus for providing a next program code word address to the read-only memory, circuits for providing an address latch enable signal to the read-only memory for latching the program code word address, circuits for providing a read signal to the read-only memory, and circuits for suppressing the address latch enable signal when the next program code word address is consecutive with an immediately preceding program code word address; and wherein the read only memory is connected to a microcontroller data bus and to the address bus, the read only memory including memory circuits for storing a sequential array of code words executable by the microcontroller, memory address decoding circuits for selecting one code word of the array of code words, circuits for conveying the selected one code word to the data bus when a read signal is received from the microcontroller, circuits for storing an address transmitted on the address bus by the microcontroller when an address latch enable signal is received from the microcontroller, the stored address being connected to the memory address decoding circuits, and circuits for incrementing the stored address each time a read signal is received from the microcontroller.
The memory circuits may include an even memory array and an odd memory array. The conveying circuits may include a multiplexer for selecting the one code word f
D'Souza Kenneth J.
Ng Tsun Yau
Bragdon Reginald G.
Shara Milad G.
Western Digital Corporation
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