High bandwidth cache system

Details High bandwidth cache system High bandwidth cache system

1998-06-08

2000-10-17

Pan, Daniel H.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710167, 712 31, G06F 1316, G06F 1320

Patent

active

061346241

ABSTRACT:
A direct access storage device (DASD) controller system for serves computer elements such as processors and disk arrays through a serial interconnect scheme. The system includes a plurality of adapters belonging to either a first set or a second set. Cache memory is divided into master memory cards and slave memory cards, each slave memory card in communication with a corresponding master memory card. A plurality of bidirectional multichannel serial data links connects one adapter with one memory card such that every adapter in the first set of adapters is connected to every master memory card and such that every adapter in the second set of adapters is connected to every slave memory card.

REFERENCES:
patent: 4430710 (1984-02-01), Catiller et al.
patent: 4520452 (1985-05-01), Loskorn
"SiI140/SiI141 Datasheet", Silicon Image, Inc. Version 1.0 Dec. 1997, Pub. # DS140/141/001-127-100.

Affiliated with

Also associated with

Rating

High bandwidth cache system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High bandwidth cache system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High bandwidth cache system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-479352