Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1997-02-19
2002-04-16
Kim, Matthew M. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S146000, C711S121000
Reexamination Certificate
active
06374329
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to providing high-availability parallel processing super servers.
SUMMARY
The present invention provides a high-availability parallel processing server that is a multi-processor computer with a segmented memory architecture. The processors are grouped into processor clusters, with each cluster consisting of up to four processors in a preferred embodiment, and there may be up to 5 clusters of processors in a preferred embodiment. Each cluster of processors has dedicated memory buses for communicating with each of the memory segments. The invention is designed to be able to maintain coherent interaction between all processors and memory segments within a preferred embodiment. A preferred embodiment uses Intel Pentium-Pro processors (hereinafter P6). The invention may be modified to utilize other processors, such as those produced by AMD or CYRIX. (Registered trademarks referenced herein belong to their respective owners.)
The present invention comprises a plurality of processor segments (a cluster of one or more CPUs), memory segments (separate regions of memory), and memory communication buses (pathways to communicate with the memory segment). Each processor segment has a dedicated communication bus for interacting with each memory segment, allowing different processors parallel access to different memory segments while working in parallel.
The processors, in a preferred embodiment, may further include an internal cache and flags associated with the cache to indicate when the data within the cache may be out of date, or if the data within the cache is data shared by other processors within the invention. Through use of setting the internal cache flag to a desired state, the contents of the internal cache of a processor may be effectively monitored from a vantage point external to the processor. This would allow for maintaining multi-processor cache coherency without requiring all processors to observe all other processors memory traffic.
The processors, in a preferred embodiment, may further comprise processors with caches external to the processor, where such cache may be an external write-back cache. There may also be caches associated with the memory communication buses to allow for enhanced memory access. In a preferred embodiment utilizing P6 processors, the processors may also be configured to operate in clusters of up to four processors to a processor segment. Note that this four processor limitation is one due to the P6 architecture. If an alternate processor is used, in which the alternate processor design allows more than four processors to a bus, then cluster size referenced herein may be adjusted accordingly.
REFERENCES:
patent: 4426688 (1984-01-01), Moxley
patent: 4484267 (1984-11-01), Fletcher
patent: 4710926 (1987-12-01), Brown et al.
patent: 4868738 (1989-09-01), Kish et al.
patent: 4934764 (1990-06-01), Leitermann et al.
patent: 5055999 (1991-10-01), Frank et al.
patent: 5077736 (1991-12-01), Dunphy, Jr. et al.
patent: 5117350 (1992-05-01), Parrish et al.
patent: 5119481 (1992-06-01), Frank et al.
patent: 5151994 (1992-09-01), Wille et al.
patent: 5226039 (1993-07-01), Frank et al.
patent: 5245563 (1993-09-01), Hauck, Jr.
patent: 5247673 (1993-09-01), Costa et al.
patent: 5251308 (1993-10-01), Frank et al.
patent: 5265235 (1993-11-01), Sindhu et al.
patent: 5274789 (1993-12-01), Costa et al.
patent: 5282201 (1994-01-01), Frank et al.
patent: 5297265 (1994-03-01), Frank et al.
patent: 5313647 (1994-05-01), Kaufman et al.
patent: 5335325 (1994-08-01), Frank et al.
patent: 5341483 (1994-08-01), Frank et al.
patent: 5341508 (1994-08-01), Keeley et al.
patent: 5352123 (1994-10-01), Sample et al.
patent: 5371896 (1994-12-01), Gove et al.
patent: 5390326 (1995-02-01), Shah
patent: 5394555 (1995-02-01), Hunter et al.
patent: 5406607 (1995-04-01), Marietta
patent: 5423037 (1995-06-01), Hvasshovd
patent: 5452447 (1995-09-01), Nelson et al.
patent: 5493728 (1996-02-01), Solton et al.
patent: 5513314 (1996-04-01), Kandasamy et al.
patent: 5560027 (1996-09-01), Watson et al.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5649194 (1997-07-01), Miller et al.
patent: 5675787 (1997-10-01), Miller et al.
patent: 5689700 (1997-11-01), Miller et al.
patent: 0 288 636 (1988-11-01), None
patent: 0 661 651 (1995-07-01), None
patent: 2171542 (1986-08-01), None
patent: 2 257 273 (1993-01-01), None
patent: WO 95/02307 (1995-01-01), None
patent: WO 95/14279 (1995-05-01), None
patent: WO 95/22111 (1995-08-01), None
patent: WO 95/25306 (1995-09-01), None
patent: WO 96/23268 (1996-08-01), None
patent: WO 96/30847 (1996-10-01), None
European Patent Office, European Search Report, Application No. EP 97 30 9471, mailed on Apr. 23, 1998, 3 pages.
Patent Cooperation Treaty, International Search Report, International Application No. PCT/US 97/21457, mailed on Apr. 23, 1998, 4 pages.
Patent Cooperation Treaty, International Search Report, International Application No. PCT/US 97/21458, mailed on Apr. 23, 1998, 3 pages.
Patent Cooperation Treaty, International Search Report, International Application No. PCT/US 97/21459, mailed on Apr. 23, 1998, 4 pages.
Patent Cooperation Treaty, International Search Report, International Application No. PCT/US 97/21460, mailed on Apr. 23, 1998, 5 pages.
Patent Cooperation Treaty, International Search Report, International Application No. PCT/US 97/21466, mailed on Apr. 23, 1998, 3 pages.
Patent Cooperation Treaty, International Search Report, International Application No. PCT/US 97/21733, mailed on Apr. 23, 1998, 3 pages.
Patent Cooperation Treaty, International Search Report, International Application No. PCT/US 97/21734, mailed on Apr. 23, 1998, 4 pages.
Anderson, T., et al. “Serverless Network File Systems,”Operating Systems Review(SIGOPS), vol. 29, No. 5, Dec. 1, 1995, pp. 109-126.
Carter, J., et al. “Network Multicomputing Using Recoverable Distributed Shared Memory,”Proceedings of the Spring Computer Society International Conference(COMPCON), San Francisco, Feb. 22-26, 1993, pp. 519-527.
Huber, J., et al. “PPFS: A High Performance Portable Parallel File System,”Proceedings of the International Conference on Supercomputing,Barcelona, Jul. 3-7, 1995, pp. 385-394.
“Java Dynamic Class Loader,”IBM Technical Disclosure Bulletin,vol. 39, No. 11, Nov. 1996, pp. 107-108.
Lee, E., et al. “Petal: Distributed Virtual Disks,”7th International Conference on Architectural Support for Programming Languages and Operation Systems,Cambridge, MA, Oct. 1-5, 1996, pp. 84-92.
Neal, D. “The Harvest Object Cache in New Zealand,”Computer Networks and ISDN Systems,vol. 11, No. 28, May 1996, pp. 1415-1430.
Raghavan, G. “A Domain Model of WWW Browsers,”Proceedings of Southeastcon, Bringing Together Education, Science and Technology,Tampa, Apr. 11-14, 1996, pp. 436-439.
Ng, T. “The Design and Implementation of a Reliable Distributed Operating System—ROSE,”Proceedings of the Symposium on Reliable Distributed Systems,Huntsville, Oct. 9-11, 1990, pp. 2-11.
Yeung, D., et al. “MGS A Multigrain Shared Memory System,”Computer Architecture News,vol. 24, No. 2, May 1, 1996, pp. 44-55.
Henskens et al. “Course and Fine Grain Objects in a Distributed Persistent Store,”Object Orientation in Operating Systems,1993, IEEE, pp. 116-123.
Amaral et al. “A Model for Persistent Shared Memory Addressing in Distributed Systems,”Object Orientation in Operating Systems,1992, IEEE, pp. 2-11.
Irelenbusch et al. “Towards a Resilient Shared Memory Concept for Distributed Persistent Object Systems,”Proceedings of the 28th Annual Hawaii Intl. Conference on System Sciences,1995, IEEE, pp. 675-684.
Lea et al. “COOL: System Support for Distributed Programming,”Communications of the ACM,vol. 36, No. 9, pp. 37-46.
Wilson, Andrew W., “Organization and Statistical Simulation of Hierarchical Multiprocessors,” UMI Dissertation Information Service (1985).
Li, Kai, “Shared Virtual Memory on Loosely Coupled Multiprocessors,” Yale University, Department of Computer Science, (Sep., 1986).
Wilson, Andrew W., “Hierachical Cache/Bus Architecture for Shared Memory Multiprocessors,”
McCarver, Jr. Charles H.
McKinney Arthur C.
Samiee Vahid
Bromberg & Sunstein LLP
Intergraph Corporation
Kim Matthew M.
Tran Denise
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