High availability error self-recovering shared cache for multipr

Details High availability error self-recovering shared cache for multipr High availability error self-recovering shared cache for multipr

1996-12-16

2000-01-11

Wright, Norman Michael

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 6, 714 48, 711130, 711142, 711150, G06F 1100

Patent

active

060147563

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD OF THE INVENTION



BACKGROUND OF THE INVENTION

The invention relates to a high availability shared cache memory in a tightly coupled multiprocessor system and, in particular, to an error self-recovery mechanism for a shared cache.
The use of shared cache memory buffers in computer systems with multiple tightly coupled processing units is known in the prior art. An exemplary approach of such a computer system is shown in FIG. 1. Herein a number of processing units P1-Pn, a shared cache memory and a main memory are interconnected by a common system bus. The processing units may further comprise so-call ed second level cache memories which are associated to the processing units. Arbitration of the main memory is accomplished by an arbiter. The shared cache is managed by means of a set associative cache directory.
A corresponding shared memory cache for the use in a multiple processor system is disclosed in EP-A-392 184. An improvement of the system's performance by means of this cache memory is achieved by: routed via the multiple processor interconnection network; network by reducing the memory access time; caches. multiprocessor systems, which supports the multiprocessor system insofar as allowing maximum parallelism in accessing the cache by the processing units, servicing one processor request in each machine cycle, reducing system response time, and increasing system throughput. The shared cache disclosed therein, uses the additional performance optimization techniques of pipelining cache operations, i.e. loads and stores, and burst-mode data accesses. By including built-in pipeline stages, that cache is enabled to service one request every machine cycle from any processing element. This contributes to reduction in the system response time as well as the throughput. Particulary one portion of the data is held by means of a logic circuitry of the cache, while another portion, corresponding to the system bus width, gets transferred to the requesting element, e.g. a processor or a storage, in one cycle. The held portion of the data can then be transferred in the following machine cycle.
Further, EP-A-0 348 628 concerns a multiprocessor system design comprising a level one cache in each processor, a shared level two cache memory, shared by each processor, and one main memory, called a level three storage. The level two cache is serial in nature. Herethrough processor requests can be partitioned into request sources, the L2 cache request priority algorithm, and status information used to control the request sources. When data is updated in the L2 cache, the other L1 caches must not see the modified data until their copies are invalidated. Hereby, storage consistency of data is accomplished.
A concept to maintain data consistency is known from an article entitled "Data Consistency in a Multi-processor System with Store-In Cache concept", Microprocessing and Microprogramming 32 (1991) 215-220, North-Holland, by G. Doettling. This article addresses the problems of maintaining data consistency in a multiprocessor system with an embedded cache on each processor. Common system resources are used to achieve data integrity under any circumstances. In particular, the so-called MESI protocol for use in multiprocessor cache structures is disclosed therein, which provides among others a Valid bit and a Multiple Copy bit for indicating the states of lines stored in the cache.
Therefore shared cache memories provide significant performance improvement for accesses to data, which is shared among the attached processing units, since those accesses do not comprise memory latency and since the shared cache provides shared data immediately.
If, for example, a processing unit requests a line which is not available in its private L2 cache, then this "request for a missing line" is routed to the shared cache and to the main memory in parallel. If the shared cache can provide the requested data, the request to the main memory will be cancelled. The main memory provides the data only in those cases where no match i

REFERENCES:
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5584013 (1996-12-01), Cheong et al.
patent: 5680577 (1997-10-01), Aden et al.
patent: 5740353 (1998-04-01), Kreulen et al.

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