Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-12-28
2003-07-15
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S152000, C711S153000
Reexamination Certificate
active
06594735
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computing systems, and more particularly to a high availability computing system having multiple processing elements capable of simultaneous execution of multiple software programs and seamless software upgrades.
BACKGROUND OF THE INVENTION
Conventional computing devices typically comprise a single central processing unit, interconnected with a single memory.
As computing demands have grown, demand for multi-processor systems has been created. A multi-processor system may execute program processes simultaneously across processors. However, multi-processor systems are very susceptible to faults in memory that is shared among the processes and processors (“shared memory”). As the shared memory is used by all processes and processors, failure of shared memory may cause failure of the entire computing system. Certain applications such as, for example, telephony switches, require extremely high availability and hence fault tolerance. A computing system offering such fault tolerance is disclosed in U.S. patent application Ser. No. 08/997,776, the contents of which are hereby incorporated by reference.
In addition to requiring fault tolerance, it may be necessary to upgrade system software from one release to the next, from time to time. In order to further achieve a high availability system, it should be possible to effect such software upgrade without significant system downtime. Accordingly, it would be beneficial if the system could execute both old and new software images simultaneously and independently to allow seamless upgrading of software.
In the past software upgrades in two processor, redundant systems have been effected by physically separating two processors operating in redundancy and associated memory, and running both with independent software loads. This facilitated the transfer of necessary operational data so that a first upgraded processor could be brought to a fully operational state while a second processor carried the processing load using old (ie. not upgraded) software. At the completion of the software upgrade of the first processor, the incoming data could be processed by the first processor running the upgraded software and the second processor could be upgraded. Once both processors were upgraded, both processors could again operate in redundancy. This approach, however, was limited to systems with two processors operating in redundancy.
Accordingly, a method and system allowing the simultaneous execution of two independent software systems on a multi-processor computing system, thereby facilitating software upgrades is desirable.
SUMMARY OF THE INVENTION
The present invention allows the separation of a computing system having at least two processing elements, and at least two memory elements into multiple logical systems. Each logical system may execute different software. Separation is accomplished by using processing elements that address memory at processor memory addresses, within a global address space. Memory elements, forming part of the system are configurable to span memory addresses within the global address space. The system may be configured into multiple logical systems by configuring one memory element to occupy address space within the global address space not used by a first of the processing elements, and configuring the another processing element to use the global address space now occupied by the configured memory element. To isolate memory elements, access to the first memory element by the second processor is limited. Two logical systems are thus formed.
Preferably, processing element memory addresses are mapped to global memory addresses by way of a configurable address mapper forming part of each processing module. Memory elements are configurable to occupy specific global addresses, by way of a memory interface. Access to memory modules may be effected by way of transactions contained in frames exchanged between processing elements and memory elements. Ports on the memory elements may be used to limit access to elements, thereby limiting access to, and isolating memory elements.
Advantageously, once a system has been separated, independent software loads may execute on the two logical systems, allowing for upgraded software to be loaded and executed on one of the two logical systems. The separated systems may then be re-combined; control of the re-combined system may be transferred to the upgraded software, thereby allowing upgrading of software executing on the original system.
REFERENCES:
patent: 3995118 (1976-11-01), Chao
patent: 4511969 (1985-04-01), Koenig et al.
patent: 4654788 (1987-03-01), Boudreau et al.
patent: 4672537 (1987-06-01), Katzman et al.
patent: 5086429 (1992-02-01), Gray et al.
patent: 5146565 (1992-09-01), Blanck et al.
patent: 5177747 (1993-01-01), Capps, Jr. et al.
patent: 5327550 (1994-07-01), Pribnow
patent: 5515523 (1996-05-01), Kalkunte et al.
patent: 5752077 (1998-05-01), Yiu et al.
patent: 5819061 (1998-10-01), Glassen et al.
patent: 5909574 (1999-06-01), Meyer
patent: 6032232 (2000-02-01), Lindeborg et al.
patent: 6105113 (2000-08-01), Schimmel
IBM Corporation, “Reliability in Multiprocessors Through Swapping Status of a Failing CPU Alternately With Status of Non Failing CPU”, IBM Technical Disclosure Bulletin, vol. 14, Issue No. 7, Dec. 1, 1971, 3 pages.
Baker Brian
Newell Terry E.
Wong Bing L.
Niebling John F.
Nortel Networks Limited
Whitmore Stacy A
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