Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2000-09-22
2002-04-02
Hudspeth, David (Department: 2651)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S154000, C714S011000
Reexamination Certificate
active
06366985
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a high availability asynchronous computer system and is particularly concerned with a system employing redundant, shared memory.
BACKGROUND OF THE INVENTION
The present invention relates to a high availability or fault tolerant memory system for a computer system. Such a computer system may be employed in telecommunications network switches, where high availability and fault tolerance is required.
In such memory systems, memory is often duplicated in shadow or mirror shared memory cards so that system performance is not halted or degraded by an error or fault in one shared memory card. It may be necessary in these systems to discover when a shared memory card has an error or fault and to diagnose the error or fault. As well, the systems need the capability to add or remove redundant shared memory cards, in order to enhance fault tolerance or eliminate excessive redundancy.
A common difficulty with systems having redundant shared memory is keeping track of how many redundant copies of data are stored and allowing a variable number of redundant copies to be stored. Many systems require a fixed number of responses to all memory requests. This reduces system flexibility and fault tolerance.
U.S. Pat. No. 4,995,040 issued Feb. 19, 1991 to Best et al. discloses a fault tolerant, fail-safe computer system including a management unit and buffer to manage asynchronous redundant digital messages, to sort the redundant messages and to compare redundant messages. The messages are compared by a majority voting scheme. The system disclosed by Best may provide high integrity but is unlikely to provide high availability or high reliability.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a high availability asynchronous memory system. A benefit of the present invention is that it allows the mirror set of redundant logical memory modules to have a variable number of logical modules. This increases system flexibility and fault tolerance.
In one aspect there is provided a method for accessing mirrored shared logical memory modules for a read including: (a) sending a memory request for a read to an interface and then to the shared logical memory modules from a requester; (b) formulating a reply at each shared logical memory module indicating whether the shared logical memory module is in a transitional state; (c) sending each reply to the interface; (d) deriving at the interface, from one or more replies, a second message; and (e) forwarding the second message to the requester from the interface.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a read including (a) sending a memory request for a read to an interface from a requester and then to the shared logical memory modules; (b) formulating a reply at each shared logical memory module indicating a size of a mirror set, where the mirror set comprises the shared logical memory modules; (c) sending each reply to the interface; (d) deriving at the interface, from one or more replies, a second message; and, (e) forwarding the second message to the requester from the interface.
In another aspect there is provided a logical shared memory module including means for receiving a memory request from another device; means for determining whether the logical shared memory module is in a transitional state; and means for generating a reply to the other device indicating whether the logical shared memory module is in a transitional state.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a write including (a) formulating a memory request for a write containing a data component to be written to a logical memory address; (b) sending the memory request for a write to an interface from a requester; (c) formulating an acceptance message indicating the memory request for a write has been accepted by the interface; (d) sending the acceptance message to the requester from the interface; (e) sending the memory request for a write to the shared logical memory modules from the interface; (f) formulating a reply, at each shared logical memory module, to the memory request for a write indicating whether the shared logical memory module is in a transitional state; and (g) sending each reply to the interface.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a write including (a) formulating a memory request for a write containing a data component to be written to a logical memory address; (b) sending the memory request for a M rite to an interface from a requester; (c) formulating an acceptance message indicating the memory request for a write has been accepted by the interface; (d) sending the acceptance message to the requester from the interface; (e) sending the memory request for a write to the shared logical memory modules from the interface; (f) formulating a reply to the memory request for a write, at each shared logical memory module, indicating a size of a mirror set, where a mirror set comprises the shared logical memory modules; and (g) sending each reply to the interface.
In another aspect there is provided a logical shared memory module comprising: means for receiving a memory request from another device; means for determining whether said logical shared memory module is in a transitional state; and, means for generating a reply to said other device indicating whether said logical shared memory module is in a transitional state.
In another aspect there is provided a method for removing a shared logical memory module from a mirror set comprising the steps: changing the shared logical memory module to a transitional state; changing the remaining shared logical memory modules to a destination set size; and disabling the shared logical memory module in said transitional state.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a write comprising the steps of: (a) formulating a memory request for a write containing a data component to be written to a logical memory address; (b) sending said memory request for a write to an interface from a requester; (c) formulating an acceptance message indicating the memory request for a write has been accepted by said interface; (d) sending said acceptance message to said requester from said interface; (e) sending said memory request for a write to at least one shared logical memory module from said interface; (f) formulating a reply to said memory request for a write indicating whether said shared logical memory module is in a transitional state; and (g) sending a reply in response to said memory request for a write from said shared logical memory module to said interface element.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a write comprising the steps of: (a) formulating a memory request for a write containing a data component to be written to a logical memory address; (b) sending said memory request for a write to an interface from a requester; (c) formulating an acceptance message indicating the memory request for a write has been accepted by said interface; (d) sending said acceptance message to said requester from said interface; (e) sending said memory request for a write to at least one shared logical memory module from said interface; (f) formulating a reply to said memory request for a write indicating a mirror set size of the shared logical memory module; and (g) sending said reply in response to said memory request for a write from said shared logical memory module to said interface element.
REFERENCES:
patent: 4995040 (1991-02-01), Best et al.
patent: 5258982 (1993-11-01), Britton et al.
patent: 5495570 (1996-02-01), Heugel et al.
patent: 5546582 (1996-08-01), Brockmeyer et al.
patent: 5615403 (1997-03-01), Bissett et al.
patent: 5625795 (1997-04-01), Sakakura et al.
patent: 5651133 (1997-07-01), Burkes et al.
patent: 5692192 (1997-11-01), Sudo
patent: 5708795 (1998-01-
Baker Brian N.
Beyerlein Ruth
Newell Terry E.
Hudspeth David
Tzeng Fred F.
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