Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1997-12-22
2001-02-06
Cabeca, John W. (Department: 2752)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S148000, C711S167000, C711S170000
Reexamination Certificate
active
06185662
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a high availability asynchronous computer system and is particularly concerned with a system employing redundant, shared memory.
BACKGROUND OF THE INVENTION
The present invention relates to a high availability or fault tolerant memory system for a computer system. Such a computer system may be employed in telecommunications network switches, where high availability and fault tolerance is required.
In such memory systems, memory is often duplicated in shadow or mirror shared memory cards so that system performance is not halted or degraded by an error or fault in one shared memory card. It may be necessary in these systems to discover when a shared memory card has an error or fault and to diagnose the error or fault. As well, the systems need the capability to add or remove redundant shared memory cards, in order to enhance fault tolerance or eliminate excessive redundancy.
A common difficulty with systems having redundant shared memory is keeping track of how many redundant copies of data are stored and allowing a variable number of redundant copies to be stored. Many systems require a fixed number of responses to all memory requests. This reduces system flexibility and fault tolerance.
U.S. Pat. No. 4,995,040 issued Feb. 19, 1991 to Best et al. discloses a fault tolerant, fail-safe computer system including a management unit and buffer to manage asynchronous redundant digital messages, to sort the redundant messages and to compare redundant messages. The messages are compared by a majority voting scheme. The system disclosed by Best may provide high integrity but is unlikely to provide high availability or high reliability.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a high availability asynchronous memory system. A benefit of the present invention is that it allows the mirror set of redundant logical memory modules to have a variable number of logical modules. This increases system flexibility and fault tolerance.
In one aspect there is provided a method for accessing mirrored shared logical memory modules for a read including sending a memory request for a read to an interface from a requester and then to the shared logical memory modules; formulating a reply at each shared logical memory module indicating a size of a mirror set, where the mirror set comprises the shared logical memory modules; formulating the reply at each shared logical memory module so as also to indicate whether each shared logical memory module is in a transitional state; formulating the reply at each shared logical memory module so as to combine indications of the size of the mirror set and indications whether each shared logical memory module is in a transitional state into a set-mode indicator; sending each reply to the interface; deriving at the interface, from one or more replies, a second message; and forwarding the second message to the requester from the interface.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a read including sending a memory request for a read to an interface and then to the shared logical memory modules from a requester; starting timers when the memory request is sent; formulating a reply at each shared logical memory module indicating whether each shared logical memory module is in a transitional state; formulating the reply at each shared logical memory module so as also to include a data component; sending each reply to the interface; deriving at the interface, from one or more replies, a second message; including a data component of one reply in the second message if each shared logical memory module is not in a transitional state; including a data component of one reply in the second message, if the timers have expired; and forwarding the second message to the requester from the interface.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a read including sending a memory request for a read to an interface and then to the shared logical memory modules from a requester; formulating a reply at each shared logical memory module indicating whether each shared logical memory module is in a transitional state; sending each reply to the interface; deriving at the interface, from one or more replies, a second message; including a data component of one reply in the second message if each shared logical memory module is not in a transitional state; forwarding the second message to the requester from the interface; and initiating an error handler if a comparison of the replies indicates an error condition.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a read including sending a memory request for a read to an interface from a requester and then to the shared logical memory modules; formulating a reply at each shared logical memory module indicating a size of a mirror set, where the mirror set comprises the shared logical memory modules; formulating the reply at each shared logical memory module so as also to include a data component; sending each reply to the interface; deriving at the interface, from one or more replies, a second message; including a data component of one reply in the second message if the size of the mirror set, as indicated in the one reply is valid; forwarding the second message to the requester from the interface; and initiating an error handler if a comparison of the replies indicates an error condition.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a read including sending a memory request for a read to an interface from a requester and then to the shared logical memory modules; formulating a reply at each shared logical memory module indicating a size of a mirror set, where the mirror set comprises the shared logical memory modules; formulating the reply at each shared logical memory module so as also to include a data component; sending each reply to the interface; deriving at the interface, from one or more replies, a second message; including a data component of one reply in the second message if the number of replies received is equivalent to the size of the mirror set; forwarding the second message to the requester from the interface; and initiating an error handler if a comparison of the replies indicates an error condition.
In another aspect there is provided a method for accessing mirrored shared logical memory modules for a read including sending a memory request for a read to an interface from a requester and then to the shared logical memory modules; formulating a reply at each shared logical memory module indicating a size of a mirror set, where the mirror set comprises the shared logical memory modules; formulating the reply at each shared logical memory module so as also to indicate whether each shared logical memory module is in a transitional state; sending each reply to the interface; deriving at the interface, from one or more replies, a second message; forwarding the second message to the requester from the interface; and initiating an error handler if a comparison of the replies indicates an error condition.
In another aspect there is provided a method for adding a new logical memory module to a mirror set, said mirror set having a mirror set logical address range, said method including (a) setting a status code of a new logical memory module to a transitional value, said new logical memory module having a logical memory module logical address range, said logical memory module logical address range being equivalent in range to said mirror set logical address range, (b) changing an indication of a size of said mirror set at existing logical memory modules to a destination set size, (c) performing a read/write march along said mirror set logical address range and (d) setting an indication of a size of said mirror set at said new logical memory module to the destination set size.
In another aspect there is provided a method for removing a
Baker Brian N.
Beyerlein Ruth
Newell Terry E.
Cabeca John W.
Nortel Networks Corporation
Tzeng Fred F.
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