Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-12-29
2001-05-08
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S711000
Reexamination Certificate
active
06228774
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to methods and apparatuses for etching through an IC's layer stack, including an oxide layer, during IC fabrication to create etched features therein.
During the manufacture of a semiconductor-based product, for example, a flat panel display or an integrated circuit, multiple deposition and/or etching steps may be employed. During the deposition step, materials are deposited onto a substrate surface (such as the surface of a glass panel or a wafer). Conversely, etching may be employed to selectively remove materials from predefined areas on the substrate surface. Etching in this manner can create etched features (such as vias, contacts, or trenches) in the oxide layer of a substrate surface wherein the etched features may be filled with metal to form a conductive path. As the term is employed herein, an oxide layer refers to a layer formed of a silicon dioxide-containing material such as TEOS (tetraethylorthosilicate), BPSG (borophosphosilicate glass), PSG (phosporous-doped silicate glass) and the like.
During etching, a mask formed of a suitable mask material, such as photoresist, is typically employed to define the areas to be etched in the oxide layer. In an exemplary photoresist technique, the photoresist material is first deposited on the oxide layer to be etched. The photoresist material is then patterned by exposing the photoresist material in a suitable lithography system, and by developing the photoresist material to form a mask to facilitate subsequent etching. Areas of the target layer (e.g., the oxide layer) that are unprotected by the mask may then be etched away using an appropriate etchant source gas, thereby forming etched features in the underlying layer.
Referring initially to
FIG. 1
a
, there is shown a layer stack
10
(not drawn to scale for ease of illustration). A substrate
20
is located at the bottom of layer stack
10
and includes a semiconductor wafer, which is typically formed of silicon. Substrate
20
may also include any other layers that may underlie an oxide layer to be etched. An oxide layer
24
is formed above substrate
20
. To create an etched feature to substrate
20
through oxide layer
24
, a layer of photoresist material is deposited and patterned using a conventional photolithography step. After patterning, an initial opening
26
is created in photoresist mask
28
to facilitate subsequent oxide etching. The above-described layers and features, as well as the processes involved in their creation, are well known to those skilled in the art.
FIG. 1
b
shows the same layer stack
10
of
FIG. 1
a
and its layers after processing. Within photoresist mask
28
, there is shown an opening
26
, which is created during the mask patterning process. Through opening
26
, etchants (or more specifically plasma formed from such etchants) react with the material of oxide layer
24
to etch features in oxide layer
24
. During this etching process, the etchants tend to anisotropically etch oxide layer
24
through opening
26
in photoresist mask
28
, forming an etched feature
30
having a diameter (or width)
32
and a depth
34
. The diameter (or width) is generally refers to as the feature size and tends to decrease with increasing circuit density. The aspect ratio is the ratio of depth to width, and tends to increase as the denominator of this ratio, i.e., the width, is decreased. After the etched feature is formed, a metal conductor may be deposited to contact the underlying layer(s) of substrate
20
through etched feature
30
.
FIG. 1
b
also depicts, as shown by the dotted lines, the layers that are also impacted by the etchants. As can be appreciated by one skilled in the art and though the illustration was not drawn to scale, photoresist layer
28
is eroded at a different rate than oxide layer
24
. Typically, the oxide layer is etched at a much faster rate than the photoresist layer. The difference between the two etching rates may be quantified by a ratio generally referred to as the oxide-to-photoresist selectivity. By way of example, if the oxide-to-photoresist selectivity 3:1, the oxide layer is etched three (3) times faster than the photoresist layer.
To achieve greater circuit density, modern integrated circuits are scaled with increasingly narrower design rules. By way of example, it is not uncommon to employ design rules as small as 0.18 microns or even smaller in the fabrication of some high density integrated circuits. As the devices are packed closer together, increased oxide-to-photoresist selectivity is needed because a thin layer of photoresist is typically applied. Further, as the width of the etched features decreases, the aspect ratio increases, necessitating a high aspect ratio etch process. Further, as the width of the etched features decreases, the need for straight side-wall profiles increase. Straight profiles ensure that the subsequently deposited metal material can properly fill the etched feature, e.g., without suffering voids due to pinch-offs, or the like.
Furthermore, current chemistries employed to etch through the oxide layer tend to be toxic to the environment. Thus, the byproduct exhaust gases tend to require extensive treatment before they can be properly discharged. Such treatment tends to require costly scrubbing devices and/or processes, which increases the final cost of the semiconductor-based products.
In view of the foregoing, there are desired improved techniques for etching features having narrow widths, high aspect ratios and straight profiles in the oxide layer.
SUMMARY OF THE INVENTION
The invention relates, in one embodiment, to a method of etching a feature in an oxide layer using a photoresist mask, the oxide layer being disposed above an underlying layer of a substrate in an inductively-coupled plasma processing chamber. The method includes flowing an etchant source gas that includes CH
2
F
2
,C
4
F
8
and O
2
into the plasma processing chamber. The method further includes forming a plasma from the etchant source gas. The method additionally includes etching through the oxide layer of the substrate with the plasma, wherein the etching substantially stops on the underlying layer, the underlying being one of a silicon layer and a tungsten-based layer.
The invention relates, in another embodiment, to a method of etching a feature in an oxide layer using a photoresist mask, the oxide layer being disposed above an underlying layer of a substrate, the substrate being disposed on an electrostatic chuck in an inductively-coupled plasma processing chamber during the etching. The method includes flowing an etchant source gas that comprises CH
2
F
2
,C
4
F
8
and O
2
into the plasma processing chamber. The method further includes forming a plasma from the etchant source gas. The method additionally includes etching through the oxide layer of the substrate with the plasma, the etching substantially stops on the underlying layer, the underlying being one of a silicon layer and a tungsten-based layer, wherein the plasma processing chamber includes a temperature-controlled top electrode, a distance between the top electrode and the electrostatic chuck is about 10 cm during the etching.
The invention relates, in another embodiment, to a method of etching a feature in an oxide layer using a photoresist mask, the oxide layer being disposed above an underlying layer of a substrate in an inductively-coupled plasma processing chamber. The method includes flowing an etchant source gas that includes C
3
H
3
F
5
,C
4
F
8
and O
2
into the plasma processing chamber. The method further includes forming a plasma from the etchant source gas. The method additionally includes etching through the oxide layer of the substrate with the plasma, wherein the etching substantially stops on the underlying layer, the underlying being one of a silicon layer and a TiN layer.
The invention relates, in yet another embodiment, to a method of etc
Beyer Weaver & Thomas LLP
Brown Charlotte A.
Lam Research Corporation
Utech Benjamin L.
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