Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-10-08
2001-05-29
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S640000, C438S673000, C438S713000
Reexamination Certificate
active
06239025
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to interconnect patterns made within high density integrated circuits. More particularly, it relates to methods and structures for forming such interconnect patterns in parallel planes.
2. Discussion of the Related Art
In current integrated circuit manufacture, there is a constant effort to create smaller and more dense circuit structures. In such dense circuit structures, it is essential to provide multiple levels of interconnect. It is commonly the practice to form a series of parallel planes of conductive material, and to make connections between those parallel planes with plugged contacts.
Integrated circuits are often operated at very high clocking speeds. Speeds of tens or hundreds of megahertz are common. The maximum attainable operating speed of a particular circuit is largely determined by the parasitic capacitance contained within its structure.
In order to reduce parasitic capacitance between the multiple levels of interconnection, there is a need to keep the parallel planes of conductive material well spaced apart. This means that thick layers of insulating material are used between the parallel planes of conductive material, and that the plugged contacts have to be deep.
The drive for increased circuit density dictates that such plugged contacts have as small a diameter (or width) as possible. Plugged contact structures are therefore required with a very high aspect ratio (height/diameter or height/width). The maximum attainable aspect ratio depends on the performance of the etch machine used to etch contact holes, and on the method used to later fill the contact holes with a conductive material. Contact holes can currently be reliably produced with aspect ratios of 4 to 5.
The minimum attainable diameter of plugged contacts depends largely on the maximum possible aspect ratio, rather than an absolute value of plugged contact diameter. Thus, it is possible to make a plugged contact of narrower diameter in a thin dielectric layer than in a thick dielectric layer. Determination of an aspect ratio of a contact hole must also take into account the thickness of any photosensitive masking layer used to define the locations in which contact holes are to be etched. In some instances, the thickness of the masking layer may be similar to the thickness of the underlying dielectric layer. Thus, if the maximum aspect ratio of the contact hole etch is 5, the final aspect ratio of the contact in the dielectric may be closer to 2.5.
As the contacts have a limited maximum aspect ratio, the joint goals of reducing parasitic capacitance by increasing dielectric layer thickness, and increasing circuit density by reducing contact diameter, are incompatible.
Contacts having high aspect ratio may be achieved using a two-step method. A first dielectric layer is etched to form contact holes, which are then filled with conductive material according to an appropriate process, to form a first layer of contacts. A second dielectric layer is then formed over the first dielectric layer and the first layer of contacts. This second dielectric layer is etched with the same pattern as the first dielectric layer. A second layer of contact holes is formed, and filled with conductive material according to an appropriate process, to form a second layer of contacts.
The overall effect of this is to double the effective maximum aspect ratio. In turn, this either allows a doubling of the spacing between subsequent parallel planes of conductive material, so reducing the parasitic capacitance; or a halving of the minimum contact diameter. Compromises may of course be used which increase the spacing between subsequent parallel planes and reduce the minimum contact diameter.
FIGS. 1
to
3
show variants of this prior art, in order to emphasize their respective drawbacks.
FIG. 1
shows a prior art structure
2
as described above. A substrate
4
contains circuitry
6
such as a MOS transistor
8
. A polysilicon line
9
is shown over a field isolation region
10
. Spacers
11
may or may not be present, adjacent to the polysilicon line
9
and the gate of transistor
8
. A first dielectric layer
12
is shown, including first contacts
13
. Above the first dielectric layer is a second dielectric layer
16
, containing second contacts
18
. Each second contact is substantially aligned with a corresponding first contact. A first metallization layer is then formed over the entire resulting upper surface, and is photolithographically patterned to form interconnect wiring
20
extending in the plane of the drawing, and interconnect wiring
21
extending perpendicularly to the plane of the drawing. In each layer
13
,
18
of contacts, the separation between adjacent contacts is governed by design rules, defined for a particular process. The minimum contact separation design rule may be determined by the possible resolution of the photolithography apparatus, or by the effectiveness of the etching apparatus used. The minimum separations are usually expressed in terms of pitch: the distance between two corresponding features on adjacent contacts with minimum separation. In
FIG. 1
, minimum design rule pitches are shown for first contact layer (d
1
) and for second contact layer (d
2
).
In two consecutive photolithographic steps, it is practically impossible to align the respective masks perfectly. For this reason, the second contacts
18
are slightly misaligned with respect to the first contacts
13
. In the figure, second contacts
18
are slightly displaced to the right. When the second dielectric layer
16
is etched, any portion of the first dielectric layer
12
exposed due to the misalignment of the two contact layers
13
,
18
is also etched. When the second contacts
18
are formed, protrusions
23
form into the first dielectric layer
12
. If the etch of the second layer
16
continues long enough, the protrusions
23
will reach the underlying circuitry
6
,
8
,
9
. This may cause voids, as the protrusion
21
is unlikely to fill entirely the hole so created. In addition, the design rules may be violated in that the minimum spacing between adjacent contacts, d
3
, is less than allowed by the design rules.
FIG. 2
shows a structure of the prior art which overcomes these problems. An intermediate metal layer is deposited over the first contact layer
13
, and etched to remain only in small pads
30
overlying each of the first contacts
13
. These pads
30
are larger than the first contacts
13
, their dimensions being sufficient that any misalignment of the second contacts
18
will not cause the second contact cut etch to attack the first dielectric layer
12
. The disadvantages of this structure are that an additional metal deposition, photolithography and etching sequence is introduced to form pads
30
. The minimum separation between adjacent contacts may now be defined in terms of the minimum possible separation d
4
of adjacent pads
30
. Due to the formation of pads
30
, the second dielectric layer
16
will be deposited with an uneven upper surface. A planarization step—either polishing, or deposition and etchback of a sacrificial layer—will be required, which adds steps to the process, and slows manufacturing.
FIG. 3
shows a structure which attempts to avoid the problems of the structure of FIG.
2
. An etch stop layer,
34
selectively etchable with respect to the material of the second dielectric layer
16
, is formed over the first dielectric layer
12
, prior to the etching of the first contact
13
holes. When the second dielectric layer
16
is etched to form the second contact
18
layer, any misalignment between the first and second contact layers will not cause the first dielectric layer
12
to be etched, as the etch will stop at the etch stop layer
34
. This structure presents the inconveniences of adding an extra layer
34
deposition, and any misalignment between corresponding second and first contacts
18
,
13
will cause a reduced surface area and so an increased resistance at their interface
36
Bease Gordon
Gayet Philippe
Chaudhari Chandra
Galanthay Theodore E.
Morris James H.
Nguyen Thanh
SGS-Thomson Microelectronics S.A.
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