High and low voltage compatible CMOS buffer

Details High and low voltage compatible CMOS buffer High and low voltage compatible CMOS buffer

1998-11-24

2000-09-19

Tokar, Michael

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 62, 257592, H03K 190175, H01L 27082

Patent

active

061217948

ABSTRACT:
A CMOS buffer circuit isolates the low voltage CMOS logic gate from high voltage components on the chip and in the environment. The CMOS buffer circuit uses high voltage npn bipolar transistors with at least two P implants in the N- well serving as the base. The processing of the npn bipolar transistors uses an extra mask for the additional P implant, but advantageously does not require a thicker oxide growth. A CMOS output buffer circuit includes two high voltage npn bipolar transistors connected between the high voltage supply, e.g., 5.0 volts, and ground. The two bipolar transistors are driven by complementary signals generated by an inverter circuit or an emitter coupled logic circuit. The inverter circuit or emitter coupled logic circuit receive an input signal from the CMOS logic gate, which is connected between the low voltage supply, e.g., 1.8 to 3.3 volts, and ground. A CMOS input buffer circuit uses a transistor--transistor logic circuit configuration connected between the high voltage supply and ground to drive the CMOS logic gate, which again is connected between the low voltage supply and ground. A resistor connected between the input terminal of the CMOS logic gate and ground is configured such that the voltage across it exceeds the switching threshold of the CMOS logic gate.

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patent: 5635860 (1997-06-01), Westerwick
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