High accuracy via formation for semiconductor devices

Details High accuracy via formation for semiconductor devices High accuracy via formation for semiconductor devices

1993-08-10

1994-06-14

Quach, T. N.

Fishing, trapping, and vermin destroying

437228, 437947, 437981, 156643, 156644, 156653, H01L 2144

Patent

active

053209818

ABSTRACT:
A semiconductor manufacturing process for forming a sloped contact in a layer of dielectric such as oxide comprises the use of an argon etchant. After a planar oxide layer is formed over a conductor, a photoresist mask defines the etch area. The exposed oxide is etched, thereby forming a sloped sidewall and a contact to the underlying conductor. This etch also forms a corner where the sloped sidewall joins the planar surface. The slope formed in the dielectric layer at this point is noncritical. After the photoresist is removed, a second etch using an inert material such as argon, krypton, or xenon is performed. This etch removes material at the corner at a rate of up to four times the removal rate at the sidewall and the planar surface. A faceted edge is thereby formed in the dielectric layer. The material that is removed to form the facet is redeposited over a portion of the sidewall and the conductive layer, and thereby improves the slope of the contact.

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