High accuracy timing model for integrated circuit verification

Details High accuracy timing model for integrated circuit verification High accuracy timing model for integrated circuit verification

2001-05-11

2004-04-13

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06721929

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention is directed toward the field of electronic design automation (“EDA”) tools, and more particularly to timing and verification techniques using a variable current source.
ART BACKGROUND
One aspect of integrated circuit design involves determining timing parameters and power consumption to characterize the chip. Currently, large scale integrated circuit (“LSI”) and very large scale integrated circuit (“VLSI”) designs are transitioning from deep submicron to ultra deep submicron (“DSM/UDSM”) feature sizes. With this transition, timing and power verification becomes more critical to achieve high electrical performance with complex integrated circuit designs. In addition to feature sizes, the accuracy of timing and power verification is also critical due to the ever-increasing size of integrated circuit designs. Furthermore, fast and accurate power and timing verification techniques are critical to meet the time to market product window demands on today's integrated circuit designs.
In general, the timing parameters define how signals propagate from one section of the chip to another. For example, timing parameters define rising signal and falling signal propagation times from drive circuits to receiver circuits in LSI/VLSI circuits. Currently, timing and power information is generated based on an instance based delay and power calculation. The delay and power calculation is formulated from a fixed library. Specifically, the library defines the pin-to-pin delay and output rise and fall times from a fixed reference lookup table of input signal slew rates and output loading capacitances. Using a fixed base library, output rise and fall times are specified based on input signal slew rates and fixed output loading capacitances.
To generate the library for timing verification, a load capacitance and input signal slew rate are used to derive the change of output voltage from the change of input voltage. However, this simple technique does not account for circuit level and device level non-linear characteristics. To further simplify the analytical requirements, the output signal curve of a device is specified as a linear sweep. With the continuing rapid advances in lithography, and as transistor dimensions become smaller, this output signal curve is dominated to a much larger extent by the transistors' nonlinear region of operation.
This prior art technique causes errors in computing both the driving instance delay and the RC network propagation delay. Specifically, these prior art linear sweep techniques cannot match actual signal curves for circuits and thus introduce unacceptable error for the delay calculation. For example, the linear sweep technique does not account for resistive shielding effects. The resistive shielding effects are caused by the resistive element in the RC network. These resistive shielding effects are amplified in DSM/UDSM designs. Thus, using these linear sweep techniques, the actual signal delay may be significantly different then the delay predictions. Accordingly, a new driving methodology is required to properly calculate delay and power results that accurately reflect the nonlinear behavior particularly found in DSM/UDSM designs.
In the DSM/UDSM designs, modeling the circuits output strength based on the change of the circuit's output voltage is critical to correctly calculating timing delay parameters and power consumption. Because traditional linear voltage sweep techniques cannot match the actual signal curves and circuits, and thus introduce unacceptable error for delay and power calculations, there is a need to more accurately model circuit characteristics based on the change of the output (driving) voltage.
SUMMARY OF THE INVENTION
A variable current source model accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive (“RC”) network, such as a wiring network that interconnects circuits in an integrated circuit. The RC network couples a driving point and a receiving point. A circuit specified in the design, such as a gate level circuit implemented in a standard cell, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point.
In one embodiment, the variable current source model operates as follows. A plurality of time instances, which correspond to a plurality of output voltages to the circuit, are specified. An initial drive current is selected, and a drive voltage, corresponding to the drive current, is determined by simulating the driving of the RC network at the driving point with the initial drive current. A load capacitance for the circuit is dynamically determined. In one embodiment, the load capacitance is determined from the charging and discharging of the RC network from the drive current. For each time instance, a new drive current for the circuit is determined from the drive voltage and the load capacitance from the previous time instance. A receiving voltage for each time instance is determined from the drive voltage and a transfer function for the RC network. The drive voltages and receiving voltages are used to generate the timing parameters of the RC network.
In one embodiment, a circuit characterization model is generated to determine, for each time instance, a new drive current from the drive voltage and the load capacitance from a prior time instance. The circuit characterization model depicts relationships among input signal slew rates, load capacitances, drive currents and drive voltages for the circuit. In one embodiment, the model is accessed to extract a drive current based on the drive voltage, effective capacitance, and the input signal slew rate selected.
The variable current model has application for calculating power, including peak power, as well as analyzing cross talk and IR drop.


REFERENCES:
patent: 5675502 (1997-10-01), Cox
patent: 5841672 (1998-11-01), Spyrou et al.
patent: 6047247 (2000-04-01), Iwanishi et al.
patent: 6269467 (2001-07-01), Chang et al.
patent: 6314546 (2001-11-01), Muddu
patent: 6476635 (2002-11-01), Rahim et al.
Shepard, KL: “Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits”, Proceeding International Conference on Computer Design VLSI in Computers and Processors, Austin, TX, Oct. 12-15, 1997pp. 532-541.
Kahng A B et al.: “Efficient gate Delay Modeling for Large Interconnect Loads”, Multi-Chip Module Conference, 1996, MCMC-96, Proceedings, 1996 IEEE Santa Cruz, CA, Feb. 6-7, 1996, pp. 202-207.

Affiliated with

Also associated with

Rating

High accuracy timing model for integrated circuit verification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High accuracy timing model for integrated circuit verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High accuracy timing model for integrated circuit verification will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3245414