Hierarchy of fault isolation timers

Details Hierarchy of fault isolation timers Hierarchy of fault isolation timers

2005-02-15

2005-02-15

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S048000

Reexamination Certificate

active

06857086

ABSTRACT:
In the present invention, a coordinated hierarchy of timing mechanisms preferably cooperate to report errors at different operational levels of a complex of computing devices. Preferably, each timer is able to identify a failure condition at its own level of operation and transmit a time-out condition to a higher level device which may also be a timer. Upon generation of a time-out condition, a system component experiencing a fault condition preferably continues to operate in a degraded mode, informs devices attempting to communicate with the faulty component of a status of the fault condition, and preferably proceeds to identify and correct a failure which caused the time out condition. The timers may be implemented in hardware or software.

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patent: 2001-350651 (2001-12-01), None

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