Hierarchical word line scheme with decoded block selecting...

Details Hierarchical word line scheme with decoded block selecting... Hierarchical word line scheme with decoded block selecting...

2003-10-01

2004-07-20

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S227000, C365S230030, C365S051000, C365S063000

Reexamination Certificate

active

06765845

ABSTRACT:

This U.S. nonprovisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application 2002-71707 filed on Nov. 18, 2002, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device and a layout method of the same which can reduce power consumption.
2. Description of Related Art
In a conventional semiconductor memory device, word lines are horizontally arranged, and bit lines are vertically arranged, and memory cells are arranged between the word lines and the bit lines. A word line is selected by decoding a row address, and a bit line is selected by decoding a column address. The bit line arranged vertically is designed to perform a voltage swing within a range of 20% of a power supply voltage. So, power consumed in the bit line is “y×C×0.2(VDD)
2
”, where C denotes a capacitance of the bit line, VDD denotes a power supply voltage, and y denotes the number of bit lines.
However, in the conventional semiconductor memory device, when one word line is selected, a charge sharing operation is performed between all memory cells connected to one word line and the bit lines, so that the number of bit lines is increased, causing an increase in power consumption.
In order to solve the problem described above, a semiconductor memory device having a divided word line structure has been introduced.
In the semiconductor memory device having the divided word line structure, a main word line and a divided word line are horizontally arranged, a bit line is vertically arranged, a memory cell is arranged between the divided word line and the bit line, and a y address word line for transmitting a block selecting signal for selecting a memory cell array block is vertically arranged. The divided word lines are divided in memory cell array block unit and selected by combining a signal for selecting the main word line and a block selecting signal for selecting a corresponding memory cell array block. So, a charge sharing operation is performed between the memory cells connected to the selected divided word line of the selected memory cell array block and the bit lines of the selected memory cell array block.
Therefore, the semiconductor memory device having the divided word line structure can reduce power consumption since only the bit lines of the selected memory cell array block perform an operation.
In general, the semiconductor memory device is designed such that the bit line arranged vertically performs a voltage swing within a range of 20% of the power supply voltage and the y address word line performs a full swing to the power supply voltage. Also, when C denotes a capacitance of the bit line, a capacitance of the y address word line is about four times as much as that of the bit line. So, when it is designed such that the memory cell array block divided into m and z memory cell arrays simultaneously selected, power consumption of the bit line is “j/m×C×0.2(VDD)
2
” and power consumption of the y address word line is “z×4C×(VDD)
2
”, where when C denotes a capacitance of the bit line, VDD denotes a power voltage, and j denotes the number of bit lines.
As a result, even though power consumption of the bit line is reduced, the semiconductor memory device having the divided word line structure has a problem in that it has higher power consumption than the general semiconductor memory devices when the number of the y address word lines is increased.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device having a divided word line structure which can reduce power consumption in a y address word line.
It is another object of the present invention to provide a layout method of a semiconductor memory device having a divided word line structure which can reduce power consumption in a y address word line.
In order to achieve the above object, the present invention provides a semiconductor memory device. In the memory device, a quantity km of memory cell array blocks are arranged in the form of k×m matrix. The memory cell array blocks are divided by a quantity x of block selecting signals and a quantity y of block selecting signals. A plurality of divided word lines are arranged horizontally. Quantity km of xy address word lines are disposed above (or below) the km memory cell array blocks. Quantity km of divided y address word lines are arranged vertically from the km xy address word lines to the km memory cell array blocks.
The present invention further provides a semiconductor memory device, comprising km memory cell array blocks arranged in the form of k×m matrix, which are divided by x block selecting signals and y block selecting signals, and which include a plurality of divided word lines arranged horizontally. A plurality of bit lines for each of the km memory cell array blocks are arranged vertically. A plurality of main word lines for a plurality of bit lines for each of the km memory cell array blocks are arranged horizontally. Quantity km of xy address word lines are disposed above or below the km memory cell array blocks. A decoding means decodes a corresponding x block selecting signal among x block selecting signals generated by decoding the x block address and y block selecting signals generated by decoding the y block address to select corresponding m xy address word lines, the decoding means being arranged for each of m memory cell array blocks arranged horizontally among the km memory cell array blocks. Quantity km of divided y address lines are arranged vertically from the km xy address word lines to the km memory cell array blocks. A word line driving means combines the plurality of the main word lines of each of the km memory cell array blocks and a signal of a corresponding xy address word line among the km xy address word lines to select the plurality of the divided word lines, the word line driving means being arranged for each of the km memory cell array block.
In one embodiment, the y block selecting signals are vertically arranged collectively on a right (or a left) side.
The present invention further provides a layout method of a semiconductor memory device. In accordance with the method, km memory cell array blocks divided by x block selecting signals and y block selecting signals are arranged in the form of a matrix. A plurality of divided word lines of each of the km memory cell array blocks are arranged horizontally. Quantity km xy address word lines are arranged above (or below) the km memory cell array blocks. Quantity km divided y address word lines are arranged vertically connected from each of the km xy address word lines on a left (or a right) side of each of the km memory cell array blocks.
The present invention further provides a layout method of a semiconductor memory device. In accordance with the method, km memory cell array blocks divided by x block selecting signals and y block selecting signals are arranged in the form of k×m matrix. A plurality of main word lines of the km memory cell array blocks are arranged horizontally; a plurality of bit lines are arranged vertically; and a plurality of divided word lines of each of the km memory cell array blocks are arranged horizontally. A quantity m of xy address word lines of m memory cell array blocks vertically arranged among the km memory cell array blocks are arranged horizontally above(or below) m memory cell array blocks arranged horizontally. A quantity y of address word lines of each of the km memory cell array blocks connected to xy address word lines of each of the km memory cell array blocks are arranged vertically on a left(or a right) side of each of the km memory cell array blocks.
In one embodiment, the y clock selecting signals are vertically arranged collectively on a right (or a left) side of the km memory cell array blocks.
In one embodiment, the method further comprises arranging, on a right

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