Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2007-09-11
2007-09-11
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S141000, C711S147000, C709S213000, C709S238000
Reexamination Certificate
active
11069848
ABSTRACT:
The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.
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Goodman James R.
Hum Herbert H. J.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen T
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