Hierarchical signal integrity analysis using interface logic...

Details Hierarchical signal integrity analysis using interface logic... Hierarchical signal integrity analysis using interface logic...

2007-05-08

2007-05-08

Do, Thuan V. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10818844

ABSTRACT:
Performing signal integrity (SI) analysis on integrated circuit designs is becoming increasingly important as these designs increase in size and complexity. Dividing a design into blocks can simplify the resulting analysis. Additionally, such blocks can be replaced with timing models, which provide a compact means of exchanging interface timing information for the blocks. To further increase the speed and accuracy of SI analysis, enhanced interface logic models (SI-ILMs) can be used. An SI-ILM can include cells in timing paths that serve as the interface between the block and other parts of the design. The SI-ILM can also include internal nets that have cross-coupling effects on interface nets and nets outside the block. By including these internal nets, SI analysis at the top-level can be both fast and accurate.

REFERENCES:
patent: 5095454 (1992-03-01), Huang
patent: 6877139 (2005-04-01), Daga
patent: 2004/0078767 (2004-04-01), Burks et al.
patent: 2004/0250224 (2004-12-01), Clement et al.
patent: 2005/0251775 (2005-11-01), Wood
Daga, Ajay J., et al. “Automated Timing Model Generation” DAC (Jun. 2002) New Orleans, LA, 6 pages.

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