Hierarchical semiconductor design

Details Hierarchical semiconductor design Hierarchical semiconductor design

1998-02-26

2002-09-10

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06449757

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the design of semiconductors, and more particularly to such design that is hierarchical in nature.
BACKGROUND OF THE INVENTION
Semiconductor technology pervades most electronic devices today. Computers, televisions, videocassette recorders, cameras, etc., all use semiconductor integrated circuits to varying degrees. For example, the typical computer includes microprocessors and dedicated controller integrated circuits (i.e., video controllers, audio controllers, etc.), as well as memory, such as dynamic random-access memory. The design of semiconductors, therefore, is a crucial consideration of the design of almost any electronic device.
One type of semiconductor design is the design of semiconductor test structures. A semiconductor integrated circuit, for example, must be able to operate in a variety of different conditions (varying temperatures, for example), and perform within a variety of different specifications (i.e., speed, power consumption, etc.). Semiconductor test structures are therefore utilized to ensure that various components of a given semiconductor will perform according to specification in different conditions. Test structures are not integrated circuits sold to end consumers as part of an electronic device, but rather are used internally to ascertain that the end products will perform correctly.
To aid in the design of semiconductors in general, and the design of semiconductor test structures in particular, software such as Design Framework II (DF2), available from Cadence Design Systems, Inc., has been developed. DF2, for example, includes an editor that permits a designer to place various components over a semiconductor substrate as necessary. DF2 also provides for a degree of flexibility in the design of such components. Specifically, DF2 includes parameterized cells, or pcells, that allow the designer to create customized instances of a pcell every time the pcell is placed on a layer. For example, a transistor can be created and have parameters assigned thereto to provide for control of its width, length, and number of gates. When instances of the transistor are placed on the layer, different values may be assigned to each of these parameters. According to the parameter values, each instance varies in size and composition.
The pcell approach of DF2, however, is a top-down semiconductor design approach, and thus has limitations and disadvantages associated with it. A designer may, for example, first draw a transistor, and then program that transistor to respond to parameters that will cause various parts of the design to take on those parameter values. This can be a very complex, tedious and error-prone process. For example, if the designer desires contacts to fill in the available active area space while maintaining a certain pitch and minimum separation from the active area edge, the equations to accomplish this for an arbitrarily sized active area are complex within DF2. Furthermore, these equations are specific to the transistor under development. If the designer desires to design another parameterized object—for example, a field transistor or a contact chain—he or she needs to repeat the entire process.
Therefore, there is a need for an approach to the designing of semiconductors that avoids the pitfalls of top-down design. The approach should enable a semiconductor designer to avoid having to “start from scratch” when designing a new parameterized object. Thus, the approach should be more flexible and easier to use than prior art design approaches.
SUMMARY OF THE INVENTION
The above-mentioned shortcomings, disadvantages and problems are addressed by the present invention, which will be understood by reading and studying the following specification. One aspect of the invention is a computerized system that includes a semiconductor structure and a basic atom. The system also includes a hierarchy of abstractions ordered from highest to lowest. Each abstraction relates a plurality of instances of an immediately lower abstraction; the highest abstraction corresponds to the structure, and the lowest abstraction corresponds to the basic atom. A plurality of sets of parameters also is included within the system, where each set of parameters corresponds to an instance of an abstraction. Changing one of the set of parameters for an instance of an abstraction changes at least one of the set of parameters for an instance of an immediately lower abstraction. Parameters desirably relate to attributes of an abstraction.
For example, in one embodiment, the hierarchy may have six abstractions: atoms, higher-order cells, devices, structures, and also circuits and integrated circuit chips, ordered from lowest to highest. Each of these abstractions has an associated set of parameters. Instances of atoms are used to create higher-order cells, instances of higher-order cells are used to create devices, and instances of devices are used to create structures. Each instance of an abstraction relates together a plurality of instances of an immediately lower-level abstraction. Thus, changing parameters associated with an instance of a higher-order cell, for example, automatically changes the parameters of the instances of atoms related by that higher-order cell.
In this manner, once appropriate atoms and higher-order cells have been designed, devices and structures can be designed easily by relating together instances of the atoms and higher-order cells. Most importantly, if the specifications governing a given structure need to be changed, a user merely has to change the parameters for the structure, which then affects the parameters of the instances of the lower level devices, higher-order cells, and atoms. That is, redesign of the structure at the atom, or even at the higher-order cell, level is not necessary. This means that semiconductor design becomes more intuitive, and enables modification of existing structures to create new structures, in a non-tedious and non-time-consuming manner.
The present invention includes computerized systems, methods, hierarchical data structures, semiconductor structures, computer-readable media, basic atom cells, and computers of varying scope. In one embodiment of the invention, the invention is implemented in conjunction with Design Framework II (DF2) software available from Cadence Design Systems, Inc. In addition to the aspects and advantages of the present invention described in this summary, further aspects and advantages of the invention will become apparent by reference to the drawings and by reading the detailed description that follows.


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