Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral monitoring
Reexamination Certificate
2000-12-11
2004-04-06
Dang, Khanh (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral monitoring
C714S025000
Reexamination Certificate
active
06718403
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of microprocessors and more particularly to a microprocessor including a performance monitor unit that uses a shared bus in conjunction with dedicated performance events signals to permit the monitoring of a wide variety of performance events while conserving the area of the layout.
2. History of Related Art
In the field of microprocessor based data processing systems, system developers strive to optimize performance and achieve the most efficient system design. Developers typically study the manner in which software programs execute instructions and access the memory hierarchy to determine the efficiency of a particular design. To aid this study, performance monitoring is typically employed. A performance monitor is generally regarded as a facility incorporated into a processor to monitor selected characteristics to assist in the debugging and analyzing of systems. Performance monitors determine machine state at a particular point in time. Often, the performance monitor produces information relating to the utilization of a processor's instruction execution and storage control. As an example, a performance monitor can be used to proceed information regarding the amount of time that has passed between events in a processing system.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a microprocessor that includes a performance monitor unit. The performance monitor unit includes a set of performance monitor counters and a corresponding set of control circuits and programmable control registers. The performance monitor unit receives a first set of event signals from functional units of the processor. Each of the first set of events is routed directly from the appropriate functional unit to the performance monitor unit. The performance monitor unit further receives at least a second set of event signals. In one embodiment, the second set of event signals is received via a performance monitor bus of the processor. The performance monitor bus is typically a shared bus that may receive signals from any of the functional units of the processor. The functional units may include multiplexing circuitry that determines which of the functional units has mastership of the shared bus. Whereas the performance monitor unit is typically capable of monitoring the direct event signals in any of its counters, the indirect event signals may be selectively routed to the counters. The shared bus may be divided into subgroups or byte lanes where the byte lanes are selectively routed to the set of performance monitor counters. The state of a control register may determine the event that is monitored in the corresponding counter. In one embodiment, the control register provides a set of signals connected to the select inputs of one or more multiplexers. The multiplexers receive multiple events signals and, based on the state of their select signals, route one of the received event signals to the corresponding performance monitor counter. Specified states of the select signals may result in the disabling of the corresponding counter or enabling the counter to count system clock cycles rather than any performance event.
REFERENCES:
patent: 6195748 (2001-02-01), Chrysos et al.
patent: 6282673 (2001-08-01), Liu et al.
Davidson Joel Roger
Laurens Judith E. K.
Mericas Alexander Erik
Dang Khanh
International Business Machines - Corporation
Lally Joseph P.
McBurney Mark E.
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