Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-02-24
2002-11-05
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S005000, C365S230030, C365S230060, C365S230080, C365S189050, C713S500000
Reexamination Certificate
active
06477630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to multi-banked dynamic random access memory (DRAM) devices and more specifically to a hierarchical row selection method and circuit for local activation of a memory array block.
2. Description of the Related Art
FIG. 1A
shows the configuration of a multiple bank 1 Gbit DRAM integrated circuit chip for purposes of illustration. This DRAM chip is not admitted to be prior art. The chip consists of eight 128 Mb double units
11
. Four 128 Mb double units
11
are arranged in each top and bottom half of the DRAM chip. The peripheral circuits
15
are located between the top and the bottom of the chip, where a plurality of address lines (i.e. 16 row address lines), a data bus (i.e. 32 data for ×32 organization), and control signals are arranged. These signals control the eight 128 Mb double-units
11
for data read and write operations. The 128 Mb double unit
11
includes two 64 Mb units
14
, a row decoder block (RDEC
10
), column decoder block (CDEC)
12
, and address pre-decoder block (PDEC)
13
.
FIG. 1B
is a detailed block diagram showing a portion of the 128 Mb double unit, in which the right 64 Mb unit and CDEC
12
are not shown for ease of illustration and explanation. The 64 Mb unit includes a plurality of the blocks
16
(e.g. 16 blocks of 4 Mb capacity each). Each block
16
includes a plurality of memory cells (for example, each block contains 4 M cells) which are arranged in x rows (e.g. 1024 rows) by y columns (e.g. 4096 columns) as is conventional in a memory array. Cells arranged in each row are coupled to the corresponding one-out-of-x wordlines (WLs), which is decoded by the corresponding one-out-of-x row decoders (RDECs)
10
A. The RDEC
10
A is driven by the predecoded addresses
22
, the drivers of which are located at the PDEC
13
. Sense amplifiers (SA)
18
are located between the adjacent blocks
16
.
FIG. 1C
is a block and circuit schematic showing a memory cell
21
within block
16
, its connection to SA
18
and the transistors which make up RDEC
10
A which drives the wordline (WL). For ease of illustration, the wordline driver has not been shown in FIG.
1
C.
The read mode operation of the circuit shown in
FIG. 1B
will now be described. When the row address strobe (RAS) signal (not shown) is enabled, the peripheral circuits
15
drive addresses
20
. The addresses
20
are predecoded by the PDEC
13
, which drives the predecoded addresses
22
. The block select signal (BLKSEL) triggers the activation of the WL by enabling RDEC
10
A. When the predecoded addresses
22
are enabled for a particular RDEC
10
A, upon receipt of the enabled BLKSEL at the RDEC
10
A, signals which activate the corresponding WL is provided to the WL driver (not shown). With the RDEC circuit scheme shown in
FIGS. 1B and 1C
, the time at which the WL starts to rise and the time at which the WL starts to fall are controlled by the leveled block select signal BLKSEL.
The BLKSEL signal is also used to activate SA
18
at a controlled time after the activation of the WL to latch the data on a complementary bitline pair (BL,/BL). An independent BLKSEL signal is generated for each block
16
. Generating the BLKSEL signal is therefore the key to controlling the block
16
to activate the WL and the SA
18
at their proper respective times.
FIG. 2A
is a block diagram showing a circuit arrangement in which predecoded addresses
22
are used as the BLKSEL signal. Such arrangement is described in detail in the article by Y. Watanabe et al entitled “A 286 mm
2
256 Mb DRAM with ×32 Both-Ends DQ,” JSSC, Vol. 31, No. 4, April 1996, pp. 567-574. The 64 Mb unit
14
includes sixteen 4 Mb blocks
16
, each block which includes 1024 WLs. In order to select and activate one wordline out of the 16,384 wordlines in the 64 Mb unit (sixteen blocks per unit ×1024 WLs per block), 14 address signals ADD<
0
:
13
> are used, where the most significant four address signals ADD<
10
:
13
> are assigned to generate the sixteen predecoded addresses. These sixteen predecoded addresses generated from ADD<
10
:
13
> are used as the BLKSEL signals to respective ones of each of the sixteen blocks
16
.
The predecoded BLKSEL scheme shown in
FIG. 2A
requires that the number of signal conductors carrying predecoded addresses
22
be increased as the number of the blocks
16
increases within the 64 Mb unit. Thirty-two BLKSEL signal conductors are required for the 128 Mb double unit
11
, requiring an area of approximately 100 um
2
, which is almost one quarter the area of the row decoder block
10
.
The scheme shown in
FIG. 2A
also requires that other predecoded addresses
22
be held in an enabled state if one of the thirty-two blocks
16
is to be activated. With such signaling scheme, it is difficult to configure the memory with multiple banks. Multi-bank organization requires that blocks be controlled independently. However, the existing signaling scheme, which requires separate predecoded address lines for each bank, requires too many signal conductors, and is therefore not practical. Thus, the existing signaling scheme is practical only for a single bank design within a 128 Mb double unit
11
.
FIG. 2B
is a block diagram showing a shared row decoder (SRDEC)
10
B which allows the predecoded addresses
24
to be shared within two 64 Mb units
14
l
and
14
r
. The predecoded addresses
24
are used to generate the BLKSEL signals. This is referred to as a predecoded block select (BLKSEL) scheme. However, the time at which the wordline (WL) starts to rise is controlled by a local block select signal (LBLKSEL) in the form of a self-resetting pulse which is triggered by BLKSEL.
The LBLKSEL signal triggers the latching of the decoded address in the SRDEC
10
B. The shared predecoded address signal lines
24
can then be used to access storage locations within the other bank. The time at which the wordline falls is controlled as in the predecoded BLKSEL approach. This makes is possible to configure the left and right 64 Mb units
14
l
and
14
r
as banks 0 and 1, respectively. However, this scheme has a similar problem to that of the decoding scheme shown in
FIG. 2A
in that the number of BLKSEL signal lines increases as the number of blocks
16
increases. In addition, the BLKSEL approach does not permit more than two banks to be configured within a single left or right unit, e.g. within either left or right 64 Mb unit shown in FIG.
2
B.
When the principle of reducing the number of timing lines shown in
FIG. 2B
is applied to a single unit containing multiple banks, a problem arises in that individual banks cannot be reset at different times. This is illustrated in the timing diagram shown in FIG.
2
C. When the precharge signal /PRG is activated, all blocks
16
are reset upon the falling edge
25
of /PRG, even though more than one bank is configured within the unit. Such simultaneous resetting contradicts the requirement that every bank be individually activated (set) and precharged (reset). The invention which will be described below overcomes this problem and allows the precharge signal to be controlled separately for each bank of a multiple bank unit of a DRAM.
By contrast, in the present invention described below, there is no limit to the number of banks which can be configured within a single left or right memory unit, for example the right 64 Mb unit
14
r
shown in FIG.
2
B. Moreover, the invention described in the following provides a way to reduce the total number of required predecoded address signal lines irrespective of the number of blocks configured within a single left or right memory unit.
Accordingly, it is an object of the present invention to provide a method of activating a wordline in a hierarchical manner.
Another object of the invention is to provide a circuit which activates a local block within a double unit
11
of a memory in a hierarchical manner.
Another object of the invention is to permit the independent activation and resetting of indi
Ji Brian
Kirihata Toshiaki
Netis Dmitry
C. Li Todd M.
McGinn & Gibb PLLC
Namazi Mehdi
Neff Daryl K.
Yoo Do Hyun
LandOfFree
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