Hierarchical partitioning

Details Hierarchical partitioning Hierarchical partitioning

2006-09-18

2009-06-30

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07555733

ABSTRACT:
Some embodiments provide a method of simulating an electrical circuit that receives a circuit description that has a set of sub-circuits. The method defines several partitions for several sub-circuits. The method then simulates the circuit using the partitioned sub-circuits. In some embodiments, the method ranks the sub-circuits prior to partitioning based on a parent-child relationship that shows how a sub-circuit is instantiated by other sub-circuits. These embodiments partition child sub-circuits first. Some embodiments provide a method of partitioning an electrical circuit that has a set of sub-circuits. For a particular sub-circuit that is instantiated from other sub-circuits, the method duplicates the particular sub-circuit into a first copy and a second copy when one port of the particular sub-circuit is connected to a voltage source in at least one instance and the same port is not connected to a voltage source in at least another instance.

REFERENCES:
patent: 6086626 (2000-07-01), Jain et al.
patent: 6577992 (2003-06-01), Tcherniaev et al.
patent: 6816826 (2004-11-01), Andersen et al.
patent: 7047510 (2006-05-01), Chopra et al.
patent: 7181708 (2007-02-01), Du et al.
patent: 2003/0163297 (2003-08-01), Khaira et al.
patent: 2004/0093571 (2004-05-01), Jain et al.
patent: 2005/0081173 (2005-04-01), Peyran
patent: 2006/0129953 (2006-06-01), Jain
patent: 2007/0044051 (2007-02-01), McGaughy et al.
U.S. Appl. No. 12/264,246, filed Nov. 3, 2008, Syed Zakir Hussain.
U.S. Appl. No. 12/264,247, filed Nov. 3, 2008, Syed Zakir Hussain.
V. Rao, D. Overhauser, I. Hajj, and T. Trick,Switch Level Timing Simulation of MOS VLSI Circuits,Boston: Kluwer Academic Publishers, pp. 30-47, 71-91, Month N/A 1989.
V. Rao and T. Trick, Network partitioning and ordering for MOS VLSI circuits,IEEE Transactions on Computer-Aided Design,vol. CAD-6, No. 1, pp. 128-144, Jan. 1987.
R. Tarjan, “Depth-first search and linear graph algorithms,”SIAM Journal of Computing,vol. 1, No. 2, pp. 146-160, Jun. 1972.

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