Hierarchical location constraints for programmable layouts

Details Hierarchical location constraints for programmable layouts Hierarchical location constraints for programmable layouts

2001-03-29

2002-11-26

Lam, Tuan T. (Department: 2816)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06487708

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to Field Programmable Gate Arrays (FPGAs). More particularly, the invention relates to methods for constraining circuit element positions in structured FPGA layouts.
BACKGROUND OF THE INVENTION
Programmable ICs are a well-known type of digital integrated circuit that may be programmed by a user to perform specified logic functions. One type of programmable IC, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
One type of FPGA, the Xilinx XC4000™ Series FPGA, is described in detail in pages 4-5 through 4-69 of the Xilinx 1998 Data Book entitled “The Programmable Logic Data Book 1998”, published in 1998 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
FIG. 1A
shows a simplified diagram of an XC4000-Series FPGA 100. The FPGA includes a uniform array of CLBs surrounded by a ring of IOBs, as described above. (The exemplary arrays herein are shown smaller than actual logic arrays in order to facilitate clear and simple drawings, but actual logic arrays typically include many more rows and columns of elements.) The CLB array typically includes variations in routing, for example at the outer edges and/or the center of the array, but the CLB array is considered uniform for purposes of this discussion because all of the logic blocks are similar. Each CLB includes two 4-input function generators, one 3-input function generator, and two flip-flops, in addition to other logic.
A more advanced FPGA is the Xilinx Virtex® FPGA, which in addition to the CLBs includes blocks of Random Access Memory (RAM). The Xilinx Virtex-II FPGA is described in detail in pages 3-75 through 3-96 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000”, published April, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
FIG. 1B
shows a simplified diagram of a Virtex FPGA
110
. The FPGA includes a uniform array of CLBs, flanked by two columns of RAM blocks, with a ring of IOBs around the CLBs and RAM blocks. The Virtex CLB is organized into two functionally similar blocks called “slices”, each of which includes two 4-input function generators and two flip-flops, in addition to other logic. The RAM blocks, of course, include different elements and are larger than the CLBs.
An even more advanced FPGA is the Xilinx Virtex®-II FPGA, which in addition to the CLBs includes blocks of Random Access Memory (RAM) and blocks implementing multiplier functions. (The Xilinx Virtex-II FPGA is described in detail in pages 33-75 of the “Virtex-II Platform FPGA Handbook”, published January, 2001, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.) The RAM and multiplier blocks are interspersed within the CLB array, forming a non-uniform array of logic blocks, as shown in FIG.
1
C.
FIG. 1C
shows a simplified diagram of a Virtex-II FPGA 120. The FPGA includes an array of CLBS, with columns of RAM blocks and multiplier blocks inserted within the CLB array. The resulting logic array is therefore non-uniform in nature, including three different kinds of logic blocks. The logic array is surrounded by a ring of IOBs, the IOB ring also including Digital Clock Manager (DCM) logic blocks. The Virtex-II FPGA also includes other types of logic blocks, but these are omitted from
FIG. 1C
for the sake of clarity. The Virtex-II CLB is organized into four slices, each of which includes two 4-input function generators and two flip-flops, in addition to other logic. Each CLB also includes two tristate buffers. The RAM blocks and multiplier blocks include different elements from the CLBs. The RAM and multiplier blocks are designed such that the height of each block is a multiple of the CLB height.
As FPGA designs increase in complexity, they reach a point at which the designer cannot deal with the entire design at the gate level. Where once a typical FPGA design comprised perhaps 5,000 gates, FPGA-designs with over 100,000 gates are now common. To deal with this complexity, circuits are typically partitioned into smaller circuits that are more easily handled. Often, these smaller circuits are divided into yet smaller circuits, imposing on the design a multi-level hierarchy of logical blocks.
Libraries of predeveloped blocks of logic have been developed that can be included in an FPGA design. Such library modules include, for example, adders, multipliers, filters, and other arithmetic and DSP functions from which complex designs can be readily constructed. The use of predeveloped logic blocks permits faster design cycles, by eliminating the redesign of duplicated circuits. Further, such blocks are typically well tested, thereby making it easier to develop a reliable complex design.
To offer the best possible performance, some library modules have a fixed size and shape, with relative location restrictions on each element. One type of module having a fixed size and shape is the Relationally Placed Macro (RPM) from Xilinx, Inc. RPMs are described in pages 4-96 and 4-97 of the “Libraries Guide” (hereinafter referred to as the “Xilinx Libraries Guide”), published October 1995 and available from Xilinx, Inc. An RPM is a schematic that includes constraints defining the order and structure of the underlying circuits. The location of each element within the RPM is defined relative to other elements in the RPM, regardless of the eventual placement of the RPM in the overall design. For example, an RPM might contain 8 flip-flops constrained to be placed into four XC4000 CLBs in a vertical column. The column of four CLBs can then be placed anywhere in any XC4000 Series FPGA.
Relative CLB locations in an RPM are specified using a Relative Location constraint called “RLOC”. RLOC constraints are described in detail in pages 4-71 through 4-95 of the Xilinx Libraries Guide.
FIG. 2A
shows how RLOC constraints are related to physical location in an array of XC4000 Series logic blocks, and how they are associated with assigned coordinates. Elements having an RLOC value of R
0
C
0
are located in a given CLB corresponding to the (
0
,
0
) coordinate location. The next CLB “below” the (
0
,
0
) CLB is designated as R
1
C
0
, corresponding to the (
0
,
1
) coordinate location. When the FPGA design is mapped and placed by the FPGA implementation tools (prior to the final routing step), these RLOC constraints are referenced and, in effect, make the RPM a “jigsaw puzzle piece” to be fitted into the FPGA along with other elements and/or modules. Although the RPM has a rigid size and shape, other logic can be placed within the borders of the RPM.
Logic can also be mapped to elements within the logic block. For example, the function generators and flip-flops inside a CLB can be directly addressed using RLOC constraints. For example, in an XC4000 Series FPGA, the “F” function generator within the (
0
,
0
) CLB is addressed by assigning the constraint “RLOC=R0C0.F” to the logic element assigned to that location. The “Y” flip-flop in the same CLB is addressed by assigning the constraint “RLOC=R0C0.FFY”, and so forth.
Some users, such as those requiring the maximum possible performance, the smallest possible implementation, or an exact pinout, want to specify exact locations for their circuit elements, rather than relative

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