Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt queuing
Patent
1996-10-09
2000-05-30
Myers, Paul R.
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt queuing
710267, 710269, 769250, 370230, G06F 1300
Patent
active
060702192
ABSTRACT:
Methods and apparatus process a plurality of interrupt status words from a network interface controller (NIC) to a plurality of processes. A first per-virtual circuit interrupt status word and a second per-virtual circuit interrupt status word can be sent by a per-virtual circuit interrupter having a per-virtual circuit interrupt output. A NIC interrupter can be in communication with the per-virtual circuit interrupt output and have a NIC interrupt output to send a first NIC interrupt status word and a second NIC interrupt status word to a global interrupt queue of a host system. The NIC interrupter can generate an interrupt signal to the host system, and a proxy interrupt handler of the host system can be in communication with the NIC interrupter. The proxy interrupt handler can awaken at least in part in response to the interrupt signal, and read the first NIC interrupt status word and the second NIC interrupt status word from the global interrupt queue, wake the first process and the second process, and send the first NIC interrupt status word to the first process and the second NIC interrupt status word to the second process.
REFERENCES:
patent: 5410708 (1995-04-01), Miyamori
patent: 5471618 (1995-11-01), Isfeld
patent: 5475860 (1995-12-01), Ellison et al.
patent: 5490134 (1996-02-01), Fernandes et al.
patent: 5524007 (1996-06-01), White et al.
patent: 5535420 (1996-07-01), Kardach et al.
patent: 5588125 (1996-12-01), Bennett
patent: 5664116 (1997-09-01), Gaytan et al.
patent: 5675829 (1997-10-01), Oskouy et al.
patent: 5682478 (1997-10-01), Watson et al.
patent: 5732082 (1998-03-01), Wartski et al.
patent: 5745790 (1998-04-01), Oskouy
patent: 5751951 (1998-05-01), Osborne et al.
patent: 5778180 (1998-07-01), Gentry et al.
patent: 5796735 (1998-08-01), Miller et al.
patent: 5802287 (1998-09-01), Rostoker et al.
patent: 5867480 (1999-02-01), Thomas et al.
PCI System Architecture Chapter 11, 1995.
McAlpine Gary Lester
Regnier Greg John
Intel Corporation
Myers Paul R.
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