Image analysis – Image compression or coding – Including details of decompression
Reexamination Certificate
1998-03-16
2002-05-21
Johnson, Timothy M. (Department: 2623)
Image analysis
Image compression or coding
Including details of decompression
C375S240120, C375S240250, C382S236000, C382S238000
Reexamination Certificate
active
06393152
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a hierarchical image processing apparatus, a hierarchical image processing method, and a data storage medium, and more particularly, to a reduction of the amount of operational processing in a processing for compressively coding digital image signals having different resolutions and in a processing for multiplexing streams obtained by compressively coding image signals having different resolutions and storing or transmitting the multiplexed streams.
Further, the present invention relates to a data storage medium for storing the multiplexed stream obtained by multiplexing the streams, and a data storage medium for storing a program which realizes, by software, the compressive coding or multiplexing that can reduce the amount of operational processing.
BACKGROUND OF THE INVENTION
As a digital image signal has huge amount of information, high coding efficiency is inevitably required to transmit or recording it. Recently, various image compressive coding techniques have been proposed, among which there is a technique carrying out hierarchical image coding which is being developed.
This technique carrying out hierarchical image coding is a method which subjects the digital image signal to compressive coding so that the user can obtain digital image signals such as the spatial-resolution image and temporal-resolution image having different resolutions from a kind of a bit stream. Such a hierarchical image coding method, for example, carries out compressive coding to the digital image data of High Definition Television (HDTV) and to the digital image data of Standard Definition Television (SDTV) simultaneously, relating them, and combines each coded image data having a different resolution to be transmitted. By this method, it is possible to regenerate digital image signal having the resolution, which the user requires, by decoding the corresponding coded image data.
A MPEG-based hierarchical image coding, which is an example of the foregoing conventional hierarchical image coding, is explained referring to figures, as follows.
FIG. 17
is a block diagram for explaining a conventional MPEG-based hierarchical coding apparatus.
This hierarchical coding apparatus
200
comprises a first compressive coding unit
1
, a first resolution conversion circuit
31
and a second compressive coding unit
2
. The first compressive coding unit
1
compressively codes an input digital image signal Sg. The first resolution conversion circuit
31
subjects the digital image signal Sg to resolution conversion in a way that its resolution is made a half both in the horizontal and vertical directions, to output a low-resolution image signal Lg. The second compressive coding unit
2
compressively codes the low-resolution image signal Lg. Before being input to the hierarchical coding apparatus
200
, the digital image signal Sg is divided into frames, and each frame is divided into coding units which are two-dimensional blocks of prescribed size.
The second compressive coding unit
2
comprises a predictive processing unit
2
a,
a subtraction processing unit
20
a,
an information compression unit
2
b,
i.e., compressive coding means, and a variable-length coding unit
23
. The predictive processing unit
2
a
receives the low-resolution image signal Lg and generating predicted data Pg
2
corresponding to the data of portion of low-resolution image signal Lg that is a target of coding (hereinafter referred to as target processing data). The subtraction processing unit
20
a
outputs either the difference between the target processing data and the predicted data Pg
2
, or the target processing unit as it is, depending on a coding mode of the digital image signal Sg. The information compression unit
2
b
subjects an output Dg
2
of the subtraction processing unit
20
a
to information compression and outputs compressed data Qg
2
. The variable-length coding unit
23
subjects the output Qg
2
of the information compression unit
2
b
to variable-length coding and outputs coded image data Eg
2
(hereinafter referred to as low-resolution coded data).
In this case, the information compression unit
2
b
comprises a DCT circuit
21
and a quantization circuit
22
. The DCT circuit
21
subjects the output data Dg
2
of the subtraction processing unit
20
a
to the Discrete Cosine Transform (DCT) which transforms data in spatial region to data in frequency region, and outputs a DCT coefficient Tg
2
. The quantization circuit
22
quantizes the DCT coefficient Tg
2
output from the DCT circuit
21
and outputs a quantization coefficient Qg
2
.
Further, the second compressive coding unit
2
comprises an information expansion unit
2
c,
i.e., decompressive decoding means, and an addition processing unit
20
b.
The information expansion unit
2
c
subjects the quantization coefficient Qg
2
output from the information compression unit
2
b
to information expansion and outputs expanded data ITg
2
. The addition processing unit
20
b
outputs either restored data Rg
2
resulting from adding the expanded data ITg
2
and the predicted data Pg
2
, or the expanded data ITg
2
as it is as restored data Rg
2
, depending on a coding mode of the digital image signal Sg. The information expansion unit
2
c
comprises an inverse quantization circuit
24
for inversely quantizing the Qg
2
output from the information compression unit
2
b,
and an inverse DCT circuit
25
for subjecting the IQg
2
output from the inverse quantization unit
24
to the inverse DCT that transforms data in frequency region to data in spatial region, and outputting the expanded data ITg
2
.
Further, the predictive processing unit
2
a
comprises a frame buffer
26
, a motion detecting circuit
28
and a motion compensation circuit
27
. The frame buffer
26
stores the restored Rg
2
output from the addition processing unit
20
b.
The motion detecting circuit
28
calculates a motion vector MV
2
corresponding to the target processing data. The motion compensation circuit
27
obtains the predicted data Pg
2
corresponding to the target processing data from the image data stored in the frame buffer
26
, based on the motion vector MV
2
from the motion detecting circuit
28
. The hierarchical coding apparatus
200
further comprises a second resolution conversion circuit
32
for converting the predicted data Pg
2
in a way to make its resolution equal to the resolution of the digital image signal Sg. The output CPg
2
of the second resolution conversion circuit
32
(hereinafter referred to as resolution converted predicted data) is output to the first compressive coding unit
1
.
The first compressive coding unit
1
has almost the same configuration as the second compressive coding unit
2
.
That is, the first compressive coding unit
1
comprises a predictive processing unit
1
a,
a subtraction processing unit
10
a,
an information compression unit
1
b,
i.e., compressive coding means, and a variable-length coding unit
13
. The predictive processing unit
1
a
receives the digital image signal Sg as a high-resolution image signal and generates predicted data Pg
1
corresponding to the data of portion of high-resolution image signal Sg that is a target of coding (hereinafter referred to as target processing data). The subtraction processing unit
10
a
outputs either the difference between the target processing data and the predicted data Pg
1
, or the target processing unit as it is, depending on a coding mode of the digital image signal Sg. The information compression unit
1
b
subjects an output Dg
1
of the subtraction processing unit
10
a
to information compression and outputs compressed data Qg
1
. The variable-length coding unit
13
subjects the output Qg
1
of the information compression unit
1
b
to variable-length coding and outputs coded image data Eg
1
(hereinafter referred to as high-resolution coded data).
In this case, the information compression unit
1
b
comprises a DCT circuit
11
and a quantization circuit
12
. The DCT circuit
11
subjects the output
Takahashi Ken'ichi
Takahashi Toshiya
Johnson Timothy M.
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
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