Hierarchical general interconnect architecture for high...

Details Hierarchical general interconnect architecture for high... Hierarchical general interconnect architecture for high...

2006-02-14

2006-02-14

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C326S037000, C326S039000

Reexamination Certificate

active

07000212

ABSTRACT:
Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a hierarchical general interconnect architecture in which: (1) reliance on single-length general interconnect lines is avoided; (2) the next greater length of general interconnect line is at least double-reach length (triple span); and (3) yet greater lengths of general interconnect line (e.g., Deca-Reach Length, or 11-span) can feed signals into logic blocks indirectly through switching resources of the shorter length, general interconnect line rather than feeding such signals directly into the logic blocks through their own respective switching resources. Additionally, the yet greater lengths of general interconnect line (e.g., Deca-Reach Length) have a fewer number of signal tap points on them than the number of logic blocks spanned by such longer ones of the general interconnect lines. Navigation limiting rules may be established to reduce the number of drive buffers needed for driving signals onto the longer ones of the general interconnect lines. In one embodiment, there are no drive buffers for middle tap points of the longer ones of the general interconnect lines.

REFERENCES:
patent: 5598346 (1997-01-01), Agrawal et al.
patent: 5883525 (1999-03-01), Tavana et al.
patent: 6118298 (2000-09-01), Bauer et al.
patent: 6130550 (2000-10-01), Zaliznyak et al.
patent: 6239613 (2001-05-01), Reddy et al.
patent: 6766505 (2004-07-01), Rangan et al.
patent: 6769107 (2004-07-01), Watkins
patent: 461798 (1991-12-01), None
patent: WO 9933177 (1999-07-01), None

Affiliated with

Also associated with

Rating

Hierarchical general interconnect architecture for high... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hierarchical general interconnect architecture for high..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchical general interconnect architecture for high... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3670861