Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-07-12
2005-07-12
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06918100
ABSTRACT:
A technique is provided for determining a hierarchical effectiveness for a cell in a data structure. The hierarchical effectiveness indicates how effective the use of the cell will be in executing a task with the data structure. A technique is also provided for determining the hierarchical effectiveness of all of the cells in a data structure, to determine which cells should be employed to execute a task with the data structure.
REFERENCES:
patent: 5790416 (1998-08-01), Norton et al.
patent: 5805860 (1998-09-01), Parham
L. G. Jones, “Fast batch incremental netlist compilation hierarchical schematics”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.: 10, Issue: 7, Jul. 1991 pp.: 922-931.
Kim et al., “Hierarchical LVS based on hierarchy rebuilding”, Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific , Feb. 10-13, 1998 pp.: 379-384.
Batra et al, “Hcompare: a hierarchical netlist comparison program”, Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE , Jun. 8-12, 1992 pp.: 299-304.
Brooks Phillip A.
Kresh Kobi
Banner & Witcoff , Ltd.
Bowers Brandon
Garbowski Leigh M.
Mentor Graphics Corp.
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