Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1999-06-10
2001-03-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S190000
Reexamination Certificate
active
06198682
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to architecture and organization of a dynamic random-access memory array and associated supporting circuitry for its high-speed reading and writing.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
The reasons often cited for the lower performance of dynamic memory arrays include the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays) and the consequential need to restore data back into each sensed memory cell during the active cycle, the need to equilibrate bit lines and various other differential nodes and to precharge various circuit nodes between active cycles, and the requirement for periodic refreshing of all dynamic memory cells.
The need for ever-increasing memory performance at reasonable cost continues unabated. It is being driven by numerous advances toward higher frequency and higher speed applications. For example, the increasing bandwidth demands of computer networking and the internet, the increasing speeds of commercially available processors, and the proliferation of high-frequency wireless communication systems are all driving the need for higher performance memory sub-systems.
In spite of the performance gains of the last 20 years, there is an unfilled need for higher performance dynamic memory arrays which leverages the lower cost-per-bit usually associated with dynamic memory arrays into the performance realm and ease of use usually associated with static memory arrays.
SUMMARY OF THE INVENTION
To provide increased performance, an amplifier in the read path, which is separate from the bit line sense amplifier, is used to develop signal on a generic I/O line before bit line sensing has occurred. The inputs of this read amplifier may be connected to the bit lines, the sense amplifier nodes, a local I/O line serving, for example, a few bit line pairs, or a local output line similarly serving, for example, a few bit line pairs. If the read amplifier inputs are connected directly to the bit line sense amplifier nodes (i.e., one read amplifier per bit line sense amplifier), the column select function may be advantageously used to enable the amplifier for the selected column, while if the read amplifier inputs are connected to local output or I/O lines (i.e., one read amplifier per group of bit line sense amplifiers), the column select friction may be used to couple the selected bit line sense amplifier to the local output or I/O lines.
In a certain embodiment of the present invention, each read amplifier's inputs are connected to the internal nodes of a corresponding bit line sense amplifier. The respective outputs of a group of read amplifiers are connected in common to a horizontally-arranged differential pair of local output lines. One such amplifier is enabled at a time by column select circuitry to develop signal on the pair of local output lines. A second stage amplifier then further buffers this signal and drives a pair of vertically-arranged global output lines. The global output lines extend the full height of the memory bank, with half preferably extending beyond the memory bank to I/O circuits above the memory bank, with the remaining half extending beyond the memory bank to I/O circuits below the memory bank. In certain embodiments, the second stage amplifier may also include a multiplexer to choose between two different pairs of local output lines (e.g., a first pair of local output lines serving 8 sense amplifiers located to the left of the second stage amplifier, and a second pair of local output lines serving 8 sense amplifiers located to the right of the second stage amplifier).
In a method embodiment of the present invention suitable for an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, a method of operating the integrated circuit includes developing on a bus a read signal for a selected memory cell substantially prior to latching a bit line sense amplifier coupled to the selected memory cell, the read signal corresponding to a voltage level previously stored within the selected memory cell.
In another embodiment of the present invention useful for an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, the integrated circuit includes: (1) a first array block including a first plurality of true and complement bit line pairs; (2) a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, for sensing a differential signal on the respective bit line pair corresponding to a voltage level previously stored within a respective memory cell of the respective bit line pair which respective memory cell is enabled by a selected word line, and for restoring a voltage level corresponding to the previously stored voltage level into the respective memory cell; (3) a first complementary pair of local bus lines associated with and traversing perpendicular to each of the first plurality of bit line pairs; (4) a first plurality of read amplifiers, each coupled to receive on a respective pair of complementary input nodes thereof a differential signal associated with a respective one of the first plurality of bit line pairs and, when selected, to drive a corresponding differential signal onto the first complementary pair of local bus lines; (5) a first complementary pair of global bus lines associated with, and traversing parallel to, the first plurality of bit line pairs and further associated with a respective plurality of bit line pairs located within respective array blocks other than the first array block; and (6) a first bus line amplifier located in close physical proximity to the first plurality of bit line sense amplifiers and arranged to receive on a first pair of complementary input nodes thereof the corresponding differential signal on the first complementary pair of local bus lines and, when selected, to drive a corresponding differential signal onto the first complementary pair of global bus lines.
In another embodiment of the present invention useful for an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each colum
Integrated Device Technology Inc.
Nelms David
Zagorin O'Brien & Graham LLP
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