Hierarchical dual bus architecture for use in an electronic swit

Details Hierarchical dual bus architecture for use in an electronic swit Hierarchical dual bus architecture for use in an electronic swit

1996-11-14

2000-04-18

Thai, Xuan M.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710128, 710131, G06F 1340

Patent

active

060527528

ABSTRACT:
A bus architecture for use in a data communication system provides a communication path between processors and one or more external devices including (M+1) hierarchical processors. Each of the processors is categorized into one of N hierarchies with M and N being a positive integer larger than 1, respectively, and N is smaller than (M+1). The bus architecture includes a bus having N buses, each of the buses coupled to one or more processors of a hierarchy and (N-1) linking means, and each of the linking means for coupling a bus of a hierarchy to a bus of a next hierarchy.

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