Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Layout generation
Reexamination Certificate
2011-07-19
2011-07-19
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Layout generation
C716S053000
Reexamination Certificate
active
07984395
ABSTRACT:
A method of increasing hierarchy compression of a metal1standard cell layout during optical proximity correction (OPC) is provided. This method can use a context determination defined from the outermost OPC correctable-edge boundaries of a metal1standard cell and not extending past outermost OPC correctable edge boundaries of adjacent metal1standard cells in other rows. The method can also include (or can alternatively include) adjusting the landing pads (resulting from metal2placement) to fit within the lines of the metal1standard cell layout. This adjusting can be performed by a place and route tool as part of a “clean-up” operation after metal2placement. The landing pads can be sized for single or double vias. A layout design for the metal1standard cell layout can be output based on using the context determination and/or adjusting the landing pads for hierarchy compression.
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Bever Hoffman & Harms LLP
Garbowski Leigh Marie
Harms Jeanette S.
Synopsys Inc.
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