Hierarchical cache system flushing scheme based on monitoring an

Details Hierarchical cache system flushing scheme based on monitoring an Hierarchical cache system flushing scheme based on monitoring an

1998-03-26

2000-09-05

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711135, 711143, G06F 1208

Patent

active

061157910

ABSTRACT:
An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.

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Intel Corp., Pentium Processor Users Manual, vol. 1: Pentium Processor Data Book-Bus Functional Description, Chapter 6, pp. 6-1 to 6-52, Apr. 1993.

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