Hierarchical cache arrangement wherein the replacement of an LRU

Details Hierarchical cache arrangement wherein the replacement of an LRU Hierarchical cache arrangement wherein the replacement of an LRU

1994-12-09

1996-12-10

Asta, Frank J.

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395446, 395448, 395451, 395457, 395463, 36424345, 36424612, 364964343, 3649662, 364DIG1, 364DIG2, G06F 1212, G06F 1300

Patent

active

055840132

ABSTRACT:
The present invention provides balanced cache performance in a data processing system. The data processing system includes a first processor, a second processor, a first cache memory, a second memory and a control circuit. The first processor is connected to the first cache memory, which serves as a first level cache for the first processor. The second processor and the first cache memory are connected to the second cache memory, which serves as a second level cache for the first processor and as a first level cache for the second processor. Replacement of a set in the second cache memory results in the set being invalidated in the first cache memory. The control circuit is connected to the second level cache and prevents replacing from a second level cache congruence class all sets that are in the first cache.

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