Hierarchical bus structure data processing apparatus and...

Details Hierarchical bus structure data processing apparatus and... Hierarchical bus structure data processing apparatus and...

1998-12-03

2001-04-24

Lee, Thomas (Department: 2782)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S120000, C710S120000, C710S120000, C711S202000

Reexamination Certificate

active

06223236

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a data processing apparatus with an input/output (I/O) device and a data processing method.
2. Description of the Related Art
An I/O device, e.g., disk controller, network controller, etc. is usually connected to a bus. Since the number of devices connectable to a bus is restricted by an electrical condition of the bus, number of control signals, etc., the number of the devices connected to the bus is limited.
The number of devices connectable to the bus can be increased by layering the bus. The layered bus is called as a hierarchical bus, hereinafter. In the hierarchical bus, a bus coupler is provided between a bus at an upper layer and a bus at a lower layer. The bus coupler relays data from a bus to an appropriate bus based on a destination address of the data transmitted in the bus.
FIG. 23
illustrates a data transfer system with the hierarchical bus according to the related art. In
FIG. 23
, disk controllers and magnetic disk drives (or also called as disk drives, hereinafter) controlled by the disk controllers are provided as the I/O devices for example. Normally, an origin or destination of a data transfer is a main memory, and the main memory is shared by all the I/O devices. Therefore, the main memory is connected to a top layer in the hierarchical bus.
Operations are explained with reference to FIG.
23
.
Data in files
61
a
-
61
f
in disk drives
8
a
-
8
f
are transferred to buffers
10
a
-
10
f
in a main memory
2
, and processed by a central processing unit (CPU)
1
.
The CPU
1
requests a disk controller
7
a
to transfer the data in the file
61
a
in the disk drive
8
a
to the buffer
10
a
. The disk controller
7
a
transfers the data to an I/O bus
5
a.
An I/O bus coupler
6
a
relays the data from the I/O bus
5
a
to an I/O bus
5
d.
A system bus-I/O bus coupler
4
relays the data from the I/O bus
5
d
to a system bus
3
. Then, the data are stored in the buffer
10
a
in the main memory
2
.
The CPU
1
also requests a disk controller
7
b
to transfer the data in the file
61
b
in the disk drive
8
b
to the buffer
10
b.
The disk controller
7
b
transfers the data to the I/O bus
5
a.
The I/O bus coupler
6
a
relays the data from the I/O bus
5
a
to the I/O bus
5
d.
The system bus-I/O bus coupler
4
relays the data from the I/O bus
5
d
to the system bus
3
. Then, the data are stored in the buffer
10
b
in the main memory
2
.
The CPU
1
also requests a disk controller
7
c
to transfer the data in the file
61
c
in the disk drive
8
c
to the buffer
10
c.
The disk controller
7
c
transfers the data to an I/O bus
5
b.
An I/O bus coupler
6
b
relays the data from the I/O bus
5
b
to the I/O bus
5
d
. The system bus-I/O bus coupler
4
relays the data from the I/O bus
5
d
to the system bus
3
. Then, the data are stored in the buffer
10
c
in the main memory
2
.
The CPU
1
also requests a disk controller
7
d
to transfer the data in the file
61
d
in the disk drive
8
d
to the buffer
10
d.
The disk controller
7
d
transfers the data to the I/O bus
5
b.
The I/O bus coupler
6
b
relays the data from the I/O bus
5
b
to the I/O bus
5
d.
The system bus-I/O bus coupler
4
relays the data from the I/O bus
5
d
to the system bus
3
. Then, the data are stored in the buffer
10
d
in the main memory
2
.
The CPU
1
also requests a disk controller
7
e
to transfer the data in the file
61
e
in the disk drive
8
e
to the buffer
10
e.
The disk controller
7
e
transfers the data to an I/O bus
5
c.
An I/O bus coupler
6
c
relays the data from the I/O bus
5
c
to the I/O bus
5
d.
The system bus-I/O bus coupler
4
relays the data from the I/O bus
5
d
to the system bus
3
. Then, the data are stored in the buffer
10
e
in the main memory
2
.
The CPU
1
also requests a disk controller
7
f
to transfer the data in the file
61
f
in the disk drive
8
f
to the buffer
10
f.
The disk controller
7
f
transfers the data to the I/O bus
5
c.
The I/C bus coupler
6
c
relays the data from the I/O bus
5
c
to the I/O bus
5
d.
The system bus-I/O bus coupler
4
relays the data from the I/C bus
5
d
to the system bus
3
. Then, the data are stored in the buffer
10
f
in the main memory
2
.
The CPU
1
processes the data transferred to the buffers
10
a
-
10
f,
and stores a result from processing in a last output buffer
101
.
As stated, the data are always transferred to the main memory
2
via the I/O bus
5
d,
system bus-I/O bus coupler
4
, and system bus
3
. The data transferred from all the I/O devices connected at lower layers in the hierarchical bus are channeled through the buses at upper layers in the hierarchical bus.
However, since data transfer in a bus per unit time is generally limited, data exceeding the limit cannot be transferred.
When a bus is occupied for a transfer of data, even if a transfer of other data is requested, the latter data cannot be transferred until the first data transfer is completed. When the data in the files
61
a
-
61
e
are transferred at once, transfer speed of the data is restricted by transfer speeds of data in the I/O bus
5
d
and system bus
3
. Therefore, even if the number of connectable devices is increased by adopting the hierarchical bus, the data transfer speed of the system is restricted by the transfer speed of the bus at the top layer. Hence, a data transfer speed appropriate for the number of devices cannot be realized.
In the hierarchical bus according to the related art, the CPU
1
processes all the data. Since the data processed by the CPU per unit time period is limited, data exceeding the limit cannot be processed. When the CPU
1
processes the data transferred from the files
61
a
-
61
e,
a processing speed of the data is restricted by the processing speed of the CPU
1
. Even if the number of connectable devices is increased by adopting the hierarchical bus, the processing speed of the system is restricted by the processing speed of the CPU, and the data processing speed appropriate for the number of devices cannot be realized.
The hierarchical bus according to the related art is configured as above stated, and all the transferred data are channeled through the buses at upper layers. Therefore, even if the number of connectable devices is increased, an appropriate data transfer speed cannot be realized.
The hierarchical bus according to the related art is configured as above stated, and the processing speed of data is restricted by the processing speed of the CPU. Therefore, even if the number of connectable devices is increased, an appropriate processing speed cannot be realized.
SUMMARY OF THE INVENTION
It is an object of this invention to solve the above-stated problems in the related art. Particularly, this invention aims at increasing the number of connectable devices by adopting a hierarchical bus and improving a transfer speed when the number of the devices is increased.
This invention also aims at increasing the number of connectable devices by adopting the hierarchical bus and improving processing speed when the number of the devices is increased.
According to one aspect of this invention, a data processing apparatus includes an upper bus and a lower bus connected hierarchically, a memory connected to the upper bus, a device connected to the lower bus, a processor, connected to the lower bus, for receiving data from the device via the lower bus, extracting a part of the received data, and transferring the extracted data to the memory via the upper bus, and a processing unit connected to the upper bus for processing the transferred data in the memory.
According to another aspect of this invention, a data processing method includes the steps of transferring data from the device to the processor via the lower bus, extracting a part of the transferred data by the processor, transferring the extracted data to the memory via the upper bus, and processing the transferred data in the memory by the processing unit.
Further features and applications of th

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