Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2006-07-31
2008-12-23
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C709S213000, C709S216000, C710S100000, C710S108000, C710S301000, C710S302000, C711S147000, C711S168000, C365S063000
Reexamination Certificate
active
07469308
ABSTRACT:
A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.
REFERENCES:
patent: 4351025 (1982-09-01), Hall, Jr.
patent: 4912633 (1990-03-01), Schweizer et al.
patent: 5586258 (1996-12-01), Conterno et al.
patent: 5734921 (1998-03-01), Dapp et al.
patent: 5752264 (1998-05-01), Blake et al.
patent: 5832216 (1998-11-01), Szczepanek
patent: 5881254 (1999-03-01), Corrigan et al.
patent: 5941973 (1999-08-01), Kondo et al.
patent: 6041379 (2000-03-01), Sher
patent: 6052752 (2000-04-01), Kwon
patent: 6055599 (2000-04-01), Han et al.
patent: 6092173 (2000-07-01), Sasaki et al.
patent: 6131153 (2000-10-01), Takamatsu
patent: 6151663 (2000-11-01), Pawlowski et al.
patent: 6167475 (2000-12-01), Carr
patent: 6205522 (2001-03-01), Hudson et al.
patent: 6212589 (2001-04-01), Hayek et al.
patent: 6339788 (2002-01-01), Geyer et al.
patent: 6351781 (2002-02-01), Gracias et al.
patent: 6393500 (2002-05-01), Thekkath
patent: 6493776 (2002-12-01), Courtright et al.
patent: 6502150 (2002-12-01), Bogin et al.
patent: 6526462 (2003-02-01), Elabd
patent: 6604159 (2003-08-01), Thekkath et al.
patent: 6628662 (2003-09-01), Blackmon et al.
patent: 6631447 (2003-10-01), Morioka et al.
patent: 6636950 (2003-10-01), Mithal et al.
patent: RE38388 (2004-01-01), Sarangdhar et al.
patent: 6721833 (2004-04-01), Lai et al.
patent: 6738845 (2004-05-01), Hadwiger et al.
patent: 6748505 (2004-06-01), Dakhil
patent: 6785793 (2004-08-01), Aboulenein et al.
patent: 6799254 (2004-09-01), Oldfield et al.
patent: 6813767 (2004-11-01), Willke
patent: 6842845 (2005-01-01), Ganapathy et al.
patent: 6892266 (2005-05-01), Reimer et al.
patent: 7107383 (2006-09-01), Rajan
patent: 7174401 (2007-02-01), Stuber et al.
patent: 2001/0003834 (2001-06-01), Shimonishi
patent: 2001/0046237 (2001-11-01), Chan et al.
patent: 2001/0054079 (2001-12-01), Hagersten et al.
patent: 2002/0194435 (2002-12-01), Yamagami et al.
patent: 2003/0097530 (2003-05-01), Arimilli et al.
Dyck Allan R.
Hobson Richard F.
Ressl Bill
Daley Christopher A
Dang Khanh
McDonnell Boehnen & Hulbert & Berghoff LLP
Schism Electronics, LLC
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