Hierarchical bitline DRAM architecture system

Details Hierarchical bitline DRAM architecture system Hierarchical bitline DRAM architecture system

2001-03-21

2002-09-24

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S230030

Reexamination Certificate

active

06456521

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a hierarchical bitline DRAM architecture system having a DRAM array which includes master and local bitlines for achieving a DRAM chip having low-power consumption, high-density and small size without affecting performance, including high random access speed and short cycle time.
BACKGROUND OF THE INVENTION
It is desirable for a memory chip to be operated at low-power. It is also desirable for the memory chip to have a high-density and a high “memory efficiency”, or small size. However, it is further desirable for the memory chip to be capable of being operated at low-power, have a high-density and small size, but without affecting performance, including high random access speed and short cycle time.
Design engineers, in an effort to improve a memory chip's characteristics without affecting the chip's performance, generally experiment with altering the size and power consumption of the chip. For example, the fast cycle DRAM approach can achieve 6 to 8 ns cycle time by using relatively small array sizes. These small arrays achieve a fast cycle time, since the bitline and wordline loading is light. However, due to the small array size, e.g., 128 wordlines by 128 pairs of bitlines, the array efficiency is very poor; the array efficiency is the ratio of array area over memory chip area. Accordingly, such small arrays require more overhead, such as support circuits, including sense amplifiers and decoders. Hence, in order to improve array efficiency for the fast cycle small array design is quite a challenge.
Prior art memory chip designs to improve array efficiency have focused on using hierarchical wordline and bitline architecture. For example, a master wordline can be coupled to a plurality of local wordline sets and a master bitline can also be coupled to a plurality of local bitline sets. Therefore, each time, only one set of bitlines and/or one set of wordlines are activated. This design methodology provides a small activated array portion while maintaining reasonable array efficiency.
With reference to
FIG. 1
, there is shown a prior art hierarchical bitline architecture system where master bitlines
10
a-d
are coupled to corresponding local bitlines. For example, master bitline
10
a
is coupled to local bitlines
20
a-d.
The primary disadvantage of this prior art system is that the master bitline
10
a
must have the same pitch size as the local bitlines
20
a-d,
since the same number of master and local bitlines are needed. If the local bitlines
20
a-d
are formed using M
1
(i.e., the first metal level) having a minimum pitch size and the master bitline
10
a
is formed by using M
3
, then the master bitline
10
a
cannot be printed with the same ground rule as the local bitlines
20
a-d.
Accordingly, the local bitlines
20
a-d
are forced to have some ground rule as that of the master bitline
20
, thereby resulting in a larger array size.
Even if one relaxes the M
1
pitch size of the local bitlines
20
a-d
to be exactly the same as the M
3
pitch size of the master bitline
10
a,
there is no space left within the chip for M
3
to be used for forming master data (or MDQ) lines, power lines, etc. This is because both M
1
and M
3
having a minimal pitch are used to form bitlines.
Another disadvantage of the prior art system shown by
FIG. 1
, is that for each pair of master bitlines
10
a-d,
a sense amplifier
30
is required. It is difficult for sense amplifiers to be laid out on the double pitch of bitlines given the fact that sense amplifiers are formed on the top and on the bottom of a DRAM array. More importantly, it is not desirable that each time a sub-array is accessed, all the sense amplifiers are activated even though only portion of the data from a sub-set of sense amplifiers is transferred out. This wastes power in conventional DRAM operation.
For example, if 2048 sense amplifiers are activated after one wordline is selected, only {fraction (1/16)} or 128 data bits are sent out. If the rest of the data bits are needed, then a page mode operation is carried out to subsequently read them all out in 15 additional cycles. Otherwise, all the data bits are just written back to the sub-arrays. Therefore, if only 128 data lines are available, the most power efficient way is just to provide 128 sense amplifiers, instead of 2048.
To achieve less number of sense amplifiers, or to share one sense amplifier with more bitlines, e.g., one sense amplifier for 16 bitline pairs, then a new system must be implemented. U.S. Pat. No. 5,394,371 issued on Feb. 28, 1995 describes a prior art system which allows for the massive sharing of sense amplifiers. U.S. Pat. No. 5,394,371 specifically teaches the concept of sharing sense amplifiers for a read only memory (ROM), such as mask ROM, where the data stored in the memory cells is non-volatile. That is, the data is not destroyed after a read operation. The data cannot be altered, except that for the mask ROM the data can be erased under UV exposure. This kind of memory is referred to as non-volatile random access memory (NVRAM).
The system described in U.S. Pat. No. 5,394,371 creates an equalization voltage using a dummy cell and then reads the data from all the cells coupled to the same wordline one-by-one sequentially. The system greatly reduces the number of sense amplifiers and eliminates power wasting by avoiding unnecessary sense amplifiers from swinging. However, the disclosed system cannot be used for DRAM, because data that is stored in a DRAM memory cell must be restored, or it could be destroyed.
In order to restore data, during a DRAM read period, there is a write-back period. The data signal that is developed and amplified in the bitlines must be stable before the data is written back to the DRAM cells.
In the system described in U.S. Pat. No. 5,394,371, the bitlines are floating after the decoder switches are shut off. At this moment, the data is not completely settled in the memory cells, since the wordline is still on. At the moment when the wordline is switching off from a boosted level (e.g., Vpp=2.5V) to ground or a negative level (e.g., Vneg=−0.5V), the strong swing of the wordline will couple all the floating bitlines lower, and it could jeopardize the “one” state signal in a DRAM cell. This coupling will do no harm to a NVRAM cell, since data is not required to be written back to the memory cells. Hence, the system described in U.S. Pat. No. 5,394,371 can only be used for NVRAMs.
SUMMARY
An aspect of the present invention is to provide a hierarchical bitline DRAM architecture system having a DRAM array which includes master and local bitlines for achieving a DRAM chip having low-power consumption, high-density and small size without affecting the chip's performance, including high random access speed and short cycle time.
Another aspect of the present invention is to provide a noise-free hierarchical bitline DRAM array which does not lose data during read/write operations.
Further, another aspect of the present invention is to provide a DRAM array having a folded-bitline differential sensing scheme and high array efficiency.
Further still, another aspect of the present invention is to provide a DRAM array having a minimum amount of sense amplifiers as compared to conventional DRAMs to save chip area and conserve power.
Further yet, another aspect of the present invention is to provide a DRAM array capable of storing data in both the single-cell and twin-cell array format, where the DRAM array is interchangeable between single-cell (for achieving high-density) and twin-cell (for consuming low-power) array operation.
Finally, another aspect of the present invention is to extend the hierarchical bitline DRAM architecture system to provide a hierarchical bitline and wordline DRAM architecture system having a DRAM array which includes master and local bitlines and master and local wordlines for achieving a DRAM chip having low-power consumption, high-d

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