Hierarchical 2T-DRAM with self-timed sensing

Details Hierarchical 2T-DRAM with self-timed sensing Hierarchical 2T-DRAM with self-timed sensing

2007-01-05

2008-12-02

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Read/write circuit

Complementing/balancing

C365S063000, C365S156000, C365S193000

Reexamination Certificate

active

07460423

ABSTRACT:
An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.

REFERENCES:
patent: 4633443 (1986-12-01), Childers
patent: 5675529 (1997-10-01), Poole
patent: 5917744 (1999-06-01), Kirihata et al.
patent: 5917745 (1999-06-01), Fujii
patent: 5973983 (1999-10-01), Hidaka
patent: 6115307 (2000-09-01), Casper
patent: 6130845 (2000-10-01), Ootsuki et al.
patent: 6278630 (2001-08-01), Yamada
patent: 6288969 (2001-09-01), Gibbins et al.
patent: RE37409 (2001-10-01), Barth et al.
patent: 6333866 (2001-12-01), Ogata
patent: 6426905 (2002-07-01), Dennard et al.
patent: 6442060 (2002-08-01), Leung et al.
patent: 6448818 (2002-09-01), Fletcher
patent: 6449201 (2002-09-01), Kojima
patent: 6456521 (2002-09-01), Hsu et al.
patent: 6542424 (2003-04-01), Endo et al.
patent: 6650572 (2003-11-01), Issa
patent: 6657886 (2003-12-01), Adams et al.
patent: 6898663 (2005-05-01), Winograd et al.
patent: 6901017 (2005-05-01), Shimizu
patent: 6998663 (2006-02-01), Yoshitomi et al.
patent: 7057230 (2006-06-01), Tanaka et al.
patent: 7082076 (2006-07-01), Terzioglu et al.
patent: 7088638 (2006-08-01), Bunce et al.
patent: 2005/0018510 (2005-01-01), Terzioglu et al.
patent: 2005/0125591 (2005-06-01), Fujimoto
patent: 2005/0141258 (2005-06-01), Kang et al.
patent: 2006/0023553 (2006-02-01), Takeyama et al.
patent: 2006/0067144 (2006-03-01), Lui
patent: 2008/0031029 (2008-02-01), Liaw
patent: 1498903 (2005-01-01), None
patent: 2004153700 (2004-05-01), None

Affiliated with

Also associated with

Rating

Hierarchical 2T-DRAM with self-timed sensing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hierarchical 2T-DRAM with self-timed sensing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchical 2T-DRAM with self-timed sensing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4052355