Hierarchic memory device having auxiliary lines connected to wor

Details Hierarchic memory device having auxiliary lines connected to wor Hierarchic memory device having auxiliary lines connected to wor

1996-09-30

1998-11-24

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, G11C 800

Patent

active

058417281

ABSTRACT:
The memory device in accordance with the present invention has hierarchical row decoding architecture and comprises at least one main decoder and a plurality of secondary decoders. The decoders have outputs coupled to a plurality of word lines respectively through a plurality of auxiliary lines having first ends respectively connected to said outputs and second ends respectively connected to intermediate points of the word lines.

REFERENCES:
patent: 4344005 (1982-08-01), Stewart
patent: 4658377 (1987-04-01), McElroy
patent: 4701885 (1987-10-01), McElroy
patent: 4800525 (1989-01-01), Shah et al.
patent: 5589699 (1996-12-01), Araki
patent: 5596542 (1997-01-01), Sugibayashi et al.
patent: 5635748 (1997-06-01), Nishizaka
Yasuhiro Hotta et al, "A 26NS 1MBit CMOS Mask ROM," IEICE Transactions, vol. E74, No. 4, 1 Apr. 1991, pp. 890-895, XP 000241311.
Fitzgerald et al., "Interwoven Word Lines on RAM Chips," IBM Technical Disclosure Bulletin, vol. 27, No. 1B, Jun. 1984, New York, US, pp. 497-498 .

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