Hiding refresh in 1T-SRAM architecture

Details Hiding refresh in 1T-SRAM architecture Hiding refresh in 1T-SRAM architecture

2006-12-05

2006-12-05

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Virtual machine memory addressing

C711S156000, C711S145000, C711S144000

Reexamination Certificate

active

07146454

ABSTRACT:
A method and device for handling the refresh requirements of a DRAM or 1-Transistor memory array such that the memory array is fully compatible with an SRAM cache under all internal and external access conditions. This includes full compatibility when sequential operations alternate between memory cells in same row and column locations within different memory banks. The device includes bi-directional buses to allow read and write operations to occur between memory banks and cache over the same bus. The refresh operations can be carried out without interference with external accesses under any conditions.

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