Hiding memory latency

Details Hiding memory latency Hiding memory latency

2008-03-15

2009-11-17

Ho, Andy (Department: 2194)

Electrical computers and digital processing systems: virtual mac

Task management or control

C717S140000, C717S146000

Reexamination Certificate

active

07620951

ABSTRACT:
An approach to hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.

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Notice of allowance for U.S. Appl. No. 11/050,020, mailed Oct. 31, 2008, 8 pages.

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