Hiding memory latency

Electrical computers and digital processing systems: virtual mac – Task management or control

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C717S140000, C717S146000

Reexamination Certificate

active

07620951

ABSTRACT:
An approach to hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.

REFERENCES:
patent: 5724565 (1998-03-01), Dubey et al.
patent: 5761515 (1998-06-01), Barton et al.
patent: 6526491 (2003-02-01), Suzuoki et al.
patent: 6549959 (2003-04-01), Yates et al.
patent: 6559854 (2003-05-01), Oka et al.
patent: 7093109 (2006-08-01), Davis et al.
patent: 2001/0002130 (2001-05-01), Suzuoki
patent: 2002/0046229 (2002-04-01), Yutaka et al.
patent: 2002/0060690 (2002-05-01), Tanaka et al.
patent: 2002/0095523 (2002-07-01), Shimakawa et al.
patent: 2002/0135582 (2002-09-01), Suzuoki et al.
patent: 2002/0138637 (2002-09-01), Suzuoki et al.
patent: 2002/0138701 (2002-09-01), Suzuoki et al.
patent: 2002/0138707 (2002-09-01), Suzuoki et al.
patent: 2002/0156993 (2002-10-01), Suzuoki et al.
patent: 2003/0055984 (2003-03-01), Shimakawa et al.
patent: 2005/0086652 (2005-04-01), Tian et al.
Notice of allowance for U.S. Appl. No. 11/050,020, mailed Oct. 31, 2008, 8 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Hiding memory latency does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hiding memory latency, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hiding memory latency will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4069711

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.