Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1990-12-21
1993-03-09
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Data refresh
365233, 36518901, C11C 1140
Patent
active
051930722
ABSTRACT:
A DRAM allows for hidden refresh of its memory cells. The refresh is performed during a refresh cycle at the beginning of a clock cycle. Immediately before the beginning of each clock cycle the DRAM selects a word line for a row of memory cells for which a data access is to be performed. The DRAM also selects at least one word line for at least one row of memory cells for which a refresh is to be performed. During the refresh cycle, a refresh is performed on every memory cell row which is selected for data access or which is selected for refresh. After the refresh cycle, during a data access segment of the clock cycle, the DRAM continues to select the word line for the row of memory cells for which a data access is to be performed; however, the DRAM no longer selects the at least one word line for at the least one row of memory cells selected for refresh. During the data access segment of the clock cycle, the data access is performed on the row of memory cells which remain selected.
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patent: 3737879 (1973-06-01), Greene et al.
patent: 4207618 (1980-07-01), White, Jr. et al.
Chu, et al, A 5V 4K.times.8 Quasi Static RAM, 1979, IEEE ISSCC, pp. 156-157.
Eaton, et al, A 100ns 64K Dynamic RAM using Redundancy Techniques, 1981, IEEE ISSCC, pp. 84, 85.
Reese, et al, A 4K.times.8 Dynamic RAM with Self Refresh, 1981, IEEE ISSCC. pp. 88, 89.
Frenkil Gerald L.
Golson Steven E.
Fears Terrell W.
VLSI Technology Inc.
Weller Douglas L.
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